Samsung's Chip Profit in a Single Year Exceeds 40 Years Combined: The AI Wave Triggers a Memory Price Crisis

A Stunning Earnings Forecast

On Reddit's r/LocalLLaMA community, a post has sparked collective anxiety among local large model enthusiasts. The title of the post is rather resigned—"Now brothers we know why we are so fucked up." Behind it lies a set of data reported by Tom's Hardware: Samsung's chip division is expected to earn more profit in a single year than the total profits of its past 40 years combined.

This is not a typo. According to the report, Samsung, riding the surge in memory and storage prices, achieved an astonishing year-over-year quarterly profit growth of roughly 19x, even surpassing NVIDIA to become the world's most profitable company. For enthusiasts who rely on large amounts of memory and VRAM to run local large language models, this news is undoubtedly a heavy blow—it directly explains why the prices of DDR5 memory, SSDs, and various storage hardware have continued to soar recently.

It's worth noting that the "19x" figure did not come out of nowhere; it is the result of starting from an extremely low base. The memory chip industry has long been known for its strong cyclicality, which the industry calls the "Silicon Cycle." This cycle is typically driven by supply-demand imbalances: when prices rise, manufacturers compete to expand capacity; years later, overcapacity leads to price collapse, prompting manufacturers to cut capital expenditure; once capacity tightens, prices rebound again, with the oscillation cycle occurring roughly every 3-5 years. In 2022-2023, the memory industry experienced a severe downturn, with giants like Samsung and SK Hynix suffering heavy losses, and some manufacturers even proactively cutting production to support prices. It was precisely from this trough, combined with the demand explosion brought by the AI wave, that the current price rebound far exceeded historical averages.

The underlying logic of the silicon cycle lies in the highly capital-intensive and relatively homogeneous nature of memory chips. Building an advanced DRAM fab requires an investment of over $20 billion, and it typically takes 3-5 years from project approval to mass production. This means manufacturers cannot quickly adjust supply based on market price signals, and once a supply-demand gap forms, it is difficult to close in the short term. Historically, the DRAM industry has experienced multiple deep downturns in 1996, 2001, 2008, 2016, and other years, with each trough accompanied by massive losses or even market exits by major manufacturers—Germany's Qimonda went bankrupt in 2009, and Japan's Elpida collapsed in 2012, both serving as cautionary tales. This high sunk cost and long capacity response cycle mean the storage industry is naturally prone to supply shortages during upswings, which in turn drives prices to overshoot.

What's worth examining more deeply is that this highly concentrated oligopoly did not happen overnight—it is the result of decades of brutal elimination rounds. In the early 1990s, there were nearly 20 DRAM manufacturers worldwide; today, Samsung, SK Hynix, and Micron together hold roughly 95% of the global DRAM market. The formation of this landscape stems both from the continuous rise in technical barriers and from deep intervention by government industrial policies. The Korean government, through low-interest loans, export subsidies, and the chaebol system, supported Samsung and SK Hynix in continuing to expand during industry troughs rather than retreating in the face of losses, ultimately squeezing European, Japanese, and Taiwanese competitors out of the market one by one through "loss-making price wars." This industrial policy logic is starkly different from the traditional Western economics narrative of "survival of the fittest"—in extremely capital-intensive industries with very high technical barriers, the continuous backing of state power is often the decisive factor in weathering cyclical troughs. The emergence of AI demand is changing this pattern: data center procurement contracts are typically multi-year, demand expectations are more stable, and the continuous and ever-expanding data center procurement demand may push traditional cyclical industries into a longer structural upcycle, giving storage manufacturers unprecedented pricing confidence.

How AI Demand Ignited the Fuse of Storage Price Hikes

From Data Centers to Your Computer

To understand why Samsung's chip profits have surged, one must return to the underlying logic of the AI industry. The demand for High Bandwidth Memory (HBM), DRAM, and large-capacity storage in large model training and inference is growing explosively. When global tech giants frantically build out data centers and snap up GPU clusters, the accompanying memory and storage chips also become scarce resources.

HBM (High Bandwidth Memory) is a new generation of memory technology designed specifically for AI accelerators and high-performance computing. Compared to traditional DRAM, HBM achieves far higher bandwidth by vertically stacking multiple layers of memory chips (3D stacking technology), connecting them via Through-Silicon Vias (TSV), and then packaging them onto the same substrate as the GPU via a silicon interposer—HBM3e can reach bandwidths of over 1.2TB/s, while ordinary DDR5 only reaches about 100GB/s. This architecture greatly shortens the data transmission path and reduces power consumption, making it a core component of NVIDIA's A100, H100, H200, and other AI training chips. From a systems architecture perspective, this design philosophy represents a paradigm shift in semiconductor packaging from "separate chips interconnected via PCB" to "heterogeneous integration connected directly via silicon substrate," whose significance extends beyond bandwidth improvement to reshaping the boundaries of entire computing systems.

HBM is far more difficult to manufacture than ordinary DRAM. The 3D stacking process requires drilling tens of thousands of through-silicon vias into extremely thin wafers and ensuring precise alignment and bonding of multiple chip layers, making yield control extremely difficult. Moreover, the silicon interposer between the HBM and GPU is itself a large, expensive precision substrate that requires advanced packaging technology to support. There is an easily overlooked bottleneck here: the CoWoS (Chip on Wafer on Substrate) process that packages HBM and GPU on the same silicon interposer is currently almost monopolized by TSMC. The core challenge of the CoWoS process is that the silicon interposer size has approached or even exceeded the exposure area of a single reticle (reticle limit), requiring stitching exposure technology, resulting in an extremely narrow process window and extremely difficult capacity expansion. In 2024, TSMC's CoWoS capacity itself was severely short, becoming one of the key constraints limiting NVIDIA's H100/H200 shipments. This means the HBM supply chain has multiple serial bottlenecks: HBM chip manufacturing, silicon interposer preparation, and advanced packaging assembly—insufficient capacity at any link affects final product delivery, making the entire AI hardware ecosystem's capacity expansion far slower than market expectations.

For this reason, only three manufacturers worldwide have the capability to mass-produce HBM—Samsung, SK Hynix, and Micron—and each faces extremely slow capacity ramp-up. This highly concentrated supply structure means HBM pricing is almost dominated by sellers; it is estimated that HBM3e's unit price is over 5-8 times that of ordinary DRAM of the same capacity.

What's worth noting is that the HBM market's oligopoly stems not only from technical difficulty but also from years of accumulated patent barriers and customer lock-in effects. SK Hynix, through deep collaboration with NVIDIA, dominates the HBM3e market with an estimated market share of over 50%; Samsung is striving to catch up; Micron is the third manufacturer with mass production capability but is relatively smaller in scale. This customer lock-in effect is not merely a business relationship but involves deep collaborative development: HBM's electrical interface specifications, package dimensions, and thermal design parameters all need to be jointly defined with GPU manufacturers, and this "co-evolution" product development model further raises supplier switching costs. Even if NVIDIA wishes to diversify supply chain risks, the actual available suppliers are extremely limited. Chinese manufacturer ChangXin Memory Technologies (CXMT) is accelerating DRAM mass production, but still lags several generations behind leaders in high-end categories such as HBM, making it difficult to break the existing landscape in the short term.

As a global leader in memory chip manufacturing, Samsung sits at the core of this supply chain. When HBM and high-end DRAM are in short supply, prices naturally rise, and Samsung's profit margins are pushed to historic highs. The so-called "19x quarterly profit growth" is precisely the direct result of this supply-demand imbalance.

The more far-reaching strategic picture is: Samsung and SK Hynix are leveraging this historic window to accelerate their transformation toward vertical integration of "storage + AI computing." SK Hynix's HBM-PIM (Processing In Memory) concept attempts to embed computing units within memory chips, fundamentally changing the von Neumann bottleneck of repeatedly shuttling data between processor and memory. The von Neumann bottleneck refers to the fact that in traditional computer architectures, the data bus bandwidth between processor and memory is far lower than the processor's computing speed, causing the CPU/GPU to waste a large amount of time waiting for data transfers. For AI inference workloads, this bottleneck is particularly pronounced—large model inference is often memory-bandwidth-limited rather than compute-limited, leaving much of the GPU's theoretical computing power idle. If PIM technology matures, it will reshape the cost structure of AI computing power at the architectural level, further consolidating the storage giants' voice in the entire AI industry chain.

The Transmission Effect of DDR5 and SSD Price Hikes

The capacity seized by AI data centers ultimately squeezes supply in the consumer market. The core resource of semiconductor manufacturing is fab capacity, measured in "wafers/month." When the profit margins of enterprise products (such as HBM and server DRAM) are significantly higher than those of consumer products (such as DDR5 memory modules and consumer SSDs), manufacturers, acting rationally, prioritize allocating limited capacity to high-margin categories. Samsung's memory chip business covers the full product line from HBM to consumer NAND, so when AI demand drives HBM and enterprise DRAM prices soaring, the internal reallocation of capacity inevitably affects consumer market supply.

There is also a key technical constraint here: DRAM and NAND Flash production lines cannot be freely interchanged. DRAM manufacturing requires high-precision multi-patterning lithography processes with extremely high equipment requirements; NAND Flash relies on vertical stacking layers to increase density, and the two differ significantly in process routes. Specifically, mainstream DRAM has advanced to the 1α nm (about 14nm) node, requiring EUV lithography equipment assistance; while NAND Flash's competitive dimension is stacking layers, with Samsung's ninth-generation V-NAND reaching over 290 layers, and competitors like Kioxia and Micron also catching up quickly. This fundamental difference in process routes means that even if Samsung is willing to expand consumer product capacity, it faces a dual bottleneck of equipment and process in the short term, making it difficult to respond quickly. Reduced supply combined with strong demand forces up the cost for ordinary consumers to buy memory and hard drives.

This is precisely the root of the wailing in the r/LocalLLaMA community. For enthusiasts who want to run 70B or even larger parameter models on home machines, memory configurations of 64GB, 128GB, or even higher are often required, and now every expansion costs far more than in the past.

The Double Dilemma of Local Large Model Enthusiasts

Hardware Barriers Keep Rising

The appeal of deploying large models locally lies in privacy, controllability, and freedom, but its hardware requirements were never low to begin with. When running large language models locally, the consumption of memory (RAM) and video memory (VRAM) is jointly determined by the model's parameter count and quantization precision. Take a common calculation as an example: a 70B parameter model, if loaded in FP16 (half-precision floating point), requires about 140GB of VRAM; even with 4-bit quantization compression, it still needs about 35-40GB. When VRAM is insufficient, the system offloads part of the model to main memory (RAM), where the capacity and bandwidth of main memory directly affect inference speed. This is also why enthusiasts in the r/LocalLLaMA community generally need 64GB or even 128GB of memory—on ordinary consumer GPUs with limited VRAM, large memory becomes a key compensation mechanism for running large-parameter models.

Quantization technology is the core barrier-lowering means for running large models locally and is worth exploring in depth. The essence of quantization is to use lower-precision numerical formats (such as INT4, INT8) to approximate model weights, thereby greatly compressing memory usage. From an information theory perspective, quantization is a form of lossy compression: original FP32 weights are represented with 32 bits, FP16 with 16 bits, INT8 with 8 bits, and INT4 with 4 bits—each drop in precision halves memory usage but introduces quantization error, affecting model output quality. Current mainstream quantization formats in the community include: GGUF (promoted by the llama.cpp project, supporting CPU inference with strong flexibility), AWQ (Activation-aware Weight Quantization, optimized for activation value distributions with smaller precision loss), and GPTQ (a quantization scheme based on layer-by-layer error compensation). AWQ's innovation lies in identifying the sensitivity differences of different weight channels to quantization error, giving higher precision protection to important channels, thereby achieving better precision retention at the same compression ratio. Additionally, ExLlamaV2 and MLC LLM are also widely adopted in specific scenarios—the former is optimized specifically for NVIDIA GPUs with extremely high inference efficiency; the latter enables cross-platform support via the TVM compiler, allowing non-mainstream hardware such as Apple Silicon and Android to run large models efficiently.

The llama.cpp project itself is a cornerstone infrastructure of the local large model community, initiated by Georgi Gerganov in early 2023. It initially only supported running LLaMA models on MacBooks but has now evolved into a complete inference engine supporting dozens of model architectures and cross-platform operation. Its core technical contributions include: implementing efficient matrix operation kernels purely in C/C++ without relying on Python runtime and CUDA; supporting hybrid CPU/GPU inference, allowing model layers to be offloaded to memory on demand; and introducing advanced quantization algorithms such as k-quant (K-means quantization) to achieve a better balance between compression ratio and precision. The toolchains formed around it—Ollama, LM Studio, Jan, and others—have greatly lowered the usage barrier for ordinary users. Notably, the server-side inference engine vLLM, with its PagedAttention mechanism, significantly leads traditional solutions in batch throughput and is becoming one of the mainstream choices for local private deployment. The core idea of PagedAttention is borrowed from the virtual memory paging management of operating systems: it splits the KV Cache (key-value cache) into fixed-size blocks, dynamically allocating and releasing them on demand, avoiding the large fragmentation waste caused by pre-allocating fixed-length VRAM in traditional solutions, thereby greatly improving the GPU's concurrent serving capacity.

However, quantization is not without cost: precision loss is particularly evident in certain tasks (such as mathematical reasoning and code generation), and aggressive quantization at the Q2 level sometimes leads to significant performance degradation or even increased hallucinations. Take GGUF's Q4_K_M quantization as an example: a 70B model can be compressed to about 40GB, enabling it to barely run on consumer machines equipped with large memory, but inference speed is still limited by memory bandwidth rather than computing power. The "Mixture of Experts" (MoE) architecture that the community is exploring is another path to reduce operating costs—by activating only some parameters for inference, models like Mixtral 8x7B achieve results close to 70B models but require only about the inference cost of a 13B model. The core mechanism of MoE is the Gating Network: after each input token is computed by a router, it is only sent to a few "expert" sub-networks for processing, while the remaining experts remain silent, keeping the inference computation controllable despite the huge parameter count. As model parameter scales continue to expand (such as Llama 3's 405B version), even after aggressive quantization, the required memory still far exceeds ordinary consumers' hardware configurations, and the hardware bottleneck always looms. The rapid evolution of software toolchains has to some extent offset the pressure of rising hardware costs, but this software-level dividend ultimately has a physical ceiling.

Beyond graphics card VRAM, the capacity of system memory often determines whether a larger model or a longer context can be loaded. Rising storage prices mean that the already-expensive "entry ticket" becomes even more costly.

A cruel reality is: the prosperity of the AI industry actually harms the interests of AI enthusiasts. Enterprise demand pushes up prices across the entire industry chain, while individual developers and researchers have to foot the bill for this prosperity. This "winner-take-all" landscape is quietly raising the barrier to the popularization of local AI.

Supply-Demand Contradictions Difficult to Ease in the Short Term

From the perspective of industry patterns, storage chip capacity expansion requires a long cycle. The R&D and construction of advanced process nodes (such as Samsung's fifth-generation V-NAND and 1Z nm-level DRAM) require multi-year cycles and tens of billions of dollars in investment, and new fabs often take 3-5 years to come online, giving extremely limited short-term production increase capability. Against the backdrop of continued high AI demand, the possibility of storage prices falling in the short term is not high. This means that local large model enthusiasts will likely still have to face high hardware costs for quite a long time to come.

The narrowing space for individuals to participate in cutting-edge AI research has been one of the core topics discussed in academia and the open-source community over the past two years. Before 2023, academic teams like Stanford's Alpaca and Berkeley's Vicuna could still fine-tune competitive models with relatively limited resources; but as base model scales broke through hundreds of billions of parameters, even fine-tuning costs exceeded the affordability of most academic institutions. This trend has sparked deep discussions in academia about the contradiction between "Democratization of Compute" and "Centralization of Compute"—the former represents the open-source community's ideal of keeping AI research barriers accessible, while the latter is the objective result of the capital-intensive AI race. Meta's open-sourcing of the Llama series is seen as a kind of counterbalance to this trend—providing high-quality base models to the community for free, allowing researchers and developers with fewer resources to still build applications on top of them. But this open-source strategy is itself controversial: when open-source models depend on the continued investment of commercial companies, their long-term independence is questionable, and the hardware costs required to run these models still form an implicit barrier to entry. Notably, the rise of parameter-efficient fine-tuning techniques such as LoRA (Low-Rank Adaptation) makes it possible to perform limited fine-tuning of large models on consumer GPUs—a pragmatic path the community has explored under hardware cost pressure. The core idea of LoRA is: the rank of the parameter update matrix during large model fine-tuning is often very low, so it can be decomposed into the product of two low-rank matrices, training only these two small matrices, thereby reducing the number of trainable parameters by hundreds of times, allowing consumer GPUs (such as the RTX 4090) to complete limited fine-tuning of billion-parameter models. Although its capability ceiling still lags noticeably behind full fine-tuning, this "trading algorithms for compute" approach represents the systematic wisdom of the open-source community in coping with hardware cost pressure.

Two Sides of the Same Coin

Samsung's chip earnings figures are one of the most vivid footnotes to the current AI era. On one hand, they confirm AI's profound pull on the entire hardware industry chain—even the traditionally highly cyclical memory chip business with huge profit volatility can rake in fortunes during this wave; on the other hand, they also reveal that the cost of this technological revolution is not evenly distributed.

For ordinary users and the open-source community, this is a warning signal worth watching. As computing power and storage become increasingly concentrated in the hands of a few giants, and as hardware costs are continuously pushed up by the AI arms race, whether individuals' space to participate in cutting-edge technology will be squeezed is worth continued attention.

Samsung surpassing NVIDIA to become the world's most profitable company marks a subtle shift in the value distribution of the AI industry—extending from chip designers to underlying material and storage suppliers. In the past, the profit high ground of the semiconductor industry was long concentrated in the chip design segment (such as Intel, Qualcomm, and NVIDIA), with manufacturing and storage manufacturers often positioned in the middle and lower reaches of the value chain. The formation of this landscape has its deep logic: chip design relies on intellectual property and talent accumulation, with near-zero marginal replication costs, exhibiting typical "winner-take-all" characteristics; while manufacturing and storage face huge fixed asset investments and fierce price competition, with profitability long under pressure. But the AI era's extreme demand for storage bandwidth and capacity has rarely given storage manufacturers near-monopoly pricing power. The deep logic of this value chain restructuring lies in the fact that AI workloads are essentially "memory-intensive" rather than purely "compute-intensive"—loading model weights, maintaining KV Cache, and accessing activation values each highly depend on the performance and capacity of the storage system. When storage becomes a systemic bottleneck, manufacturers that master core storage technology and capacity naturally gain bargaining power exceeding their traditional position. And part of the bill for this feast ultimately falls on every ordinary person who wants to embrace local AI.

Key Takeaways