Cerebras CEO to Discuss the Limits of AI Compute Scaling at TechCrunch Disrupt

Can AI Keep Scaling?

At the upcoming TechCrunch Disrupt 2026 conference, Cerebras Systems co-founder and CEO Andrew Feldman will address one of the industry's most pressing questions: given the relentlessly rising demands on compute, energy, and infrastructure, will today's AI hardware eventually hit a scaling wall — and if so, where does the industry go from there?

The topic resonates deeply because AI model capabilities over the past few years have been largely driven by what's known as "scaling" — bigger models, more data, more compute. But as model parameter counts grow exponentially, the compute, power, and data center infrastructure required to support training and inference are coming under mounting pressure. Feldman's talk will focus on these constraints themselves, and on the alternative path Cerebras is pursuing.

Cerebras's Differentiated Approach

Cerebras has carved out a distinctive position in AI hardware with its Wafer-Scale Engine (WSE). Rather than combining multiple chips through high-speed interconnects — as traditional GPU clusters do — Cerebras fabricates a single massive chip across an entire silicon wafer, integrating an enormous number of compute cores and on-chip memory within a single die. This design philosophy is itself an answer to the question of how to break through compute scaling bottlenecks.

A central theme of Feldman's talk will be how Cerebras views the triple constraints of compute, energy, and infrastructure differently from the mainstream. While the industry at large debates how to stack more GPUs and build ever-larger data centers, Cerebras's approach leans toward redefining the efficiency and density of compute units at the chip architecture level — seeking greater effective throughput within the same energy and physical footprint.

The core breakthrough of the Wafer-Scale Engine lies in eliminating the inter-chip interconnect bottleneck inherent in conventional multi-chip designs. Standard GPU servers must transfer data across hundreds or thousands of chips using high-speed interconnect protocols like NVLink and InfiniBand — a process that consumes substantial bandwidth, introduces significant latency, and adds power overhead. Cerebras's WSE integrates hundreds of billions of transistors onto a single silicon wafer roughly the size of an A4 sheet of paper. Its third-generation WSE-3 features over 4 trillion transistors and 900,000 AI compute cores, enabling all core-to-core communication to occur entirely on-chip, with memory bandwidth reaching tens of TB/s — far exceeding the cross-node bandwidth of GPU clusters. This architecture is particularly effective for large model inference, since LLM inference is typically memory-bandwidth-bound rather than compute-bound, allowing the on-chip high-bandwidth memory advantage to be fully realized.

The Triple Challenge: Compute, Energy, and Infrastructure

The constraints facing the AI industry today are not one-dimensional. Compute supply is limited by advanced-node manufacturing capacity and chip supply chains; energy has become an increasingly acute concern, with power consumption from large AI training clusters now a critical factor in site selection and operations; and the construction timelines and costs associated with data center infrastructure are further constraining the rapid deployment of compute.

These three factors are deeply intertwined, forming the practical ceiling on AI scaling. Feldman's talk is expected to dissect the nature of these bottlenecks and explore whether, as the traditional dividends of Moore's Law diminish and the marginal returns from simply adding more hardware decline, the industry needs to pursue new breakthroughs in architectural innovation, energy efficiency, or even at the algorithmic level.

The "diminishing returns of Moore's Law" must be understood in context: the rate of transistor density improvement has slowed from doubling every two years to roughly every three to four years, and as process nodes push below 3nm, physical limits such as quantum tunneling make leakage current increasingly problematic — meaning the performance and efficiency gains from shrinking process nodes are experiencing diminishing returns. Meanwhile, Dennard scaling (the principle that power density remains constant as transistors shrink) broke down in the mid-2000s, directly causing the thermal design power (TDP) of modern high-end AI accelerators to exceed 400W or even 700W. When individual chips can no longer achieve significant gains through process upgrades alone, stacking more chips becomes the dominant path — but this simultaneously intensifies system-level challenges around data center cooling, power delivery density, and interconnect latency.

What Happens If Hardware Hits Its Limits?

The most forward-looking part of the discussion will be a consideration of what happens if today's AI hardware reaches its limits. This question cuts to the heart of the industry's long-term trajectory: does it continue relying on hardware scaling, or pivot toward more efficient model designs, sparsity techniques, and specialized accelerator architectures as alternative paths?

As the head of a company that has staked its identity on disruptive hardware architecture, Feldman's perspective represents one interpretation of this question from the hardware innovation camp. For practitioners and investors focused on AI infrastructure, the chip industry, and the sustainable development of large models, this conversation offers an important lens through which to understand the industry's future direction.

An Industry Signal Worth Watching

The conversation set to take place at TechCrunch Disrupt 2026 is, at its core, a public examination of whether the "AI scaling narrative" can continue. It serves as a reminder to the industry that ongoing advances in AI capabilities are not a given — they rest on the practical foundation of whether compute, energy, and infrastructure can keep pace.

Regardless of where the answers ultimately land, the architectural innovation path represented by Feldman and Cerebras will remain an indispensable force in the AI hardware race. The value of this discussion lies not only in illuminating today's bottlenecks, but in sketching out a possible path forward for the entire industry.