Former Intel CEO Slams HBM: High Bandwidth Flash Could Be the Replacement

HBM Faces Industry Skepticism

With AI chips exhibiting a near-insatiable appetite for memory bandwidth, High Bandwidth Memory (HBM) was once seen as the defining solution to the "memory wall" problem. But a growing chorus of industry voices is challenging that narrative. In recent public discussions, former Intel CEO Pat Gelsinger flatly declared "HBM is lousy," while industry analyst firm Irrational Analysis went further with the pointed assessment: "HBM is a mistake."

What makes this particularly striking is that the skepticism isn't coming solely from competitors or outside observers. A vice president at SK Hynix — one of HBM's primary suppliers — has also acknowledged: "HBM is not the final answer to the memory wall problem." When upstream suppliers start leaving room in the conversation to question their own flagship products, it's a signal that the debate over memory architecture has entered genuinely uncharted territory.

HBM's core design philosophy involves stacking multiple DRAM dies vertically using TSV (Through-Silicon Via) technology, then integrating them alongside a GPU or AI accelerator on a shared substrate (interposer) via 2.5D packaging. This drastically shortens the physical distance between memory and compute, while dramatically increasing the number of connection pins — delivering bandwidth far beyond what traditional GDDR memory can offer. HBM3e can exceed 1.2 TB/s of peak bandwidth, compared to roughly 1 TB/s for GDDR6X. Leading AI training cards like NVIDIA's H100 rely on HBM as their primary memory, where its high-bandwidth characteristics are critical for memory-intensive operations like matrix multiplication. Because HBM is so deeply embedded in today's AI infrastructure, any serious questioning of its roadmap reverberates across the entire chain — from chip design to data center procurement.

The Technical Paradox of "Stacking Higher"

The crux of the debate is HBM's evolutionary direction: increasing capacity and bandwidth by vertically stacking more DRAM dies. But the higher you stack, the more apparent the problems become.

A key contradiction critics point to: "If you stack enough layers… each individual core die ends up running slower than ordinary commodity memory." The logic here is that as bandwidth gets distributed across more and more stacked layers, the effective throughput available to each individual layer is severely diluted.

At the Hot Chips 2026 Q&A session, Irrational Analysis posed a pointed question that cut to the heart of the matter: "You're talking about HBM4 being stacked 20 dies high, perhaps achieving 4 TB per square centimeter of capacity. But that means each of those 20 layers only gets about 20% of a single die's bandwidth. You're diluting your throughput very heavily. Why is this the right direction? Why are you so focused on stacking memory higher rather than making it faster?"

This question strikes directly at the vulnerability in HBM's evolutionary roadmap — that in the race for capacity, the industry may be sacrificing per-unit-storage performance efficiency.

Understanding the "bandwidth dilution" critique requires appreciating HBM's physical structural constraints. TSV technology drills vertical channels through chips and fills them with conductive material to interconnect layers, but TSV density and signal integrity have engineering limits. As stack counts grow from 8 layers in HBM2 to the 16–20 layers planned for HBM4, the base logic die at the bottom must simultaneously drive I/O for all DRAM layers above it — while the total external interface bandwidth doesn't scale proportionally. In other words, external bandwidth is determined by packaging pin count, not layer count; but capacity grows linearly with layers, causing the bandwidth-to-capacity ratio to continuously decline. For AI inference workloads, if model weight retrieval is bottlenecked by this diluted per-layer bandwidth, the capacity gains from adding layers may not offset the efficiency losses — which is precisely the "cost-performance trap" critics are describing.

High Bandwidth Flash: The Next Alternative?

One concept that keeps surfacing in these discussions is "High Bandwidth Flash." This term hints at an emerging direction: combining NAND flash media with high-bandwidth interfaces to redefine the memory hierarchy for AI computing.

From a technology evolution standpoint, flash memory has natural advantages over DRAM in capacity density and cost. If bandwidth and latency bottlenecks can be addressed and flash can be integrated into HBM-like packaging configurations, it could theoretically deliver a more cost-effective solution for scenarios like large-model inference, where capacity is the dominant constraint. That said, flash memory's write endurance, latency characteristics, and fundamental operating principles differ substantially from DRAM — whether it can truly handle AI training and inference workloads remains to be proven by real-world products.

It's worth emphasizing that these discussions remain at the level of architectural debate and roadmap speculation. No mature, production-ready products are available for direct comparison yet.

NAND flash and DRAM differ fundamentally at the physics level: DRAM stores data via capacitor charge and discharge, with read/write latency around 60–100 nanoseconds. NAND flash stores charge in floating gates or charge traps, with read latency typically in the 10–100 microsecond range — and writes involve block erase operations with even higher latency and limited write endurance (TBW). For "High Bandwidth Flash" to occupy the primary memory slot in an AI accelerator, substantial innovation would be required at the interface protocol and controller level to mask flash's inherent high latency, while achieving aggregate bandwidth through massive parallelism (many dies reading simultaneously). Current industry explorations include CXL (Compute Express Link) memory expansion and processing-in-memory architectures, but no mature solution has yet demonstrated the ability to compete head-to-head with HBM under the random access patterns of AI training. Inference workloads — particularly weight loading for large models — follow more regular access patterns, and are widely considered the most likely entry point for flash-based approaches to gain a foothold.

Industry Signals Behind the Debate

This wave of HBM criticism reveals several noteworthy trends in the broader industry landscape.

First, the explosive growth of AI compute has made memory cost an increasingly large share of total system cost, and HBM's premium pricing is now under scrutiny. Critics have predicted: "Soon we'll all look back and wonder why people paid such high prices for something so inefficient." This reflects growing market frustration with the gap between HBM's pricing and its actual efficiency.

Second, divisions within the supplier ecosystem suggest that memory architecture is far from settled. SK Hynix's executive comments indicate that even stakeholders with a direct financial interest in HBM are leaving room for a pivot, rather than betting everything on the stacking roadmap.

Third, the fact that top chip conferences like Hot Chips are becoming public battlegrounds for this architectural debate signals that the question has escalated from an engineering detail to a strategic choice.

That said, a measured perspective is warranted: HBM remains the de facto standard for AI accelerators today and is unlikely to be displaced in the near term. These critiques are more of a warning signal about long-term technical direction than an immediate rejection of the status quo. Whether High Bandwidth Flash can deliver on its promise ultimately depends on measured performance data and real-world deployment at scale.

Final Thoughts

From celebrated solution to the memory wall, to being called "inefficient" — HBM's reputation has undergone a subtle but meaningful shift in just a few years. This debate, involving a former Intel CEO, independent analysts, and even suppliers themselves, is fundamentally asking: when it comes to meeting the memory demands of the AI era, is stacking higher really the only right path forward?

The answer may not come until High Bandwidth Flash and other alternatives produce real, shipping products. Until then, maintaining a healthy skepticism toward any single technology narrative is essential for anyone following the AI hardware space.