Kirin 9050 Enters Mass Production: A Teardown of Huawei's First Logic-Folding Chip

Huawei revealed the technical details of the Kirin 9050 series at its Terminal Innovation Technology Briefing, with the most closely watched item being the first mass-produced logic-folding chip, the Kirin 9050 Pro. This technology changes how a chip is laid out, and it directly shapes how the Mate 90 series performs in on-device AI, imaging, and display.

What Logic Folding Actually Changes

Traditional chip design essentially unfolds on a two-dimensional plane, with functional modules arranged along that plane, so data must travel relatively long paths to reach compute units. The Kirin 9050 Pro takes a completely different approach: the team started from a three-dimensional perspective, treating multiple dies as a single complete chip in a co-design process, layering them according to logical relationships, and then connecting the layers with dense vertical interconnects.

This corresponds to Huawei's proposed Tao's Law—shifting the focus of innovation to time scaling, improving system efficiency by compressing the time spent on signal propagation and computation waiting. For a chip, the speed of the transistors themselves and the speed at which data reaches the compute units together determine final performance, and logic folding targets the latter half.

50 Million Hybrid Bonds Are the Prerequisite for Mass Production

For circuits to truly fold, inter-layer interconnects must be dense enough. The Kirin 9050 series has an interconnect scale exceeding 50 million hybrid bonds and more than 5 million effective signal interconnects, providing sufficient communication channels for cross-layer layouts.

Xu Songyu, Director of Product Management for Wireless Terminal Chips in Huawei's Semiconductor Business, said that the Kirin 9050 Pro has a top metal pitch of 720 nanometers, and this generation's hybrid bonding pitch reaches 1.5 micrometers. According to Huawei's research, a ratio of hybrid bonding pitch to top metal pitch of less than 3 is an important condition for achieving effective logic folding.

This ratio says one thing: design freedom depends on manufacturing capability. Only when the bonding pitch shrinks further can more connections be provided per unit area, and only then do more logic modules have the opportunity to participate in cross-layer layout. The 53.5% increase in transistor density Huawei announced is a resulting metric, but the briefing did not give a conclusion on the equivalent process node corresponding to the cross-layer layout.

Top Metal Pitch refers to the center-to-center distance between adjacent wires in the uppermost metal routing layer of a chip. In advanced logic processes, the lower metal layers are used for transistor-level fine-grained wiring, while the top metal layer is used for global power distribution and long-distance signal transmission, so the top metal pitch is usually noticeably larger than the lower layers.

This parameter is repeatedly mentioned because it determines how dense the chip's "loosest" routing layer can be: the top metal layer is responsible for sending signals from one end of the chip to the other. If it is too sparse, the path savings from cross-layer layout will be offset by long-distance detours. Huawei announced that the Kirin 9050 Pro has a top metal pitch of 720 nanometers, while the hybrid bonding pitch reaches 1.5 micrometers, giving a ratio of about 2.08, which satisfies the "less than 3" condition. This means the connection density provided by bonding is already higher than the routing density required by the top metal layer, so cross-layer interconnects will not become the weak link limiting design freedom, and only then does logic folding become feasible for mass production.

Performance Data and Real-World Gains

According to figures released by Huawei, compared with the Mate 80 Pro Max equipped with the Kirin 9030 Pro, the Mate 90 Pro Max equipped with the Kirin 9050 Pro achieves clear improvements through logic folding and a new-generation architecture optimization: CPU frequency up 12.7%, CPU performance up 25%, GPU performance up 40% with power consumption down 45%, and NPU compute up 140% with power consumption down 66%.

Behind these numbers is an easily overlooked mechanism: cross-layer layout shortens clock routing, improves clock skew, and reduces clock tree depth, thereby cutting clock distribution overhead. Once the critical path is improved, it also creates the conditions for lowering operating voltage and saving power.

Take the CPU subsystem as an example. There is a typical critical path between CPU cores and L1/L2 cache. Logic folding allows the relevant circuits to be laid out across two layers and connected through hybrid bonding, creating room to raise frequency. This means that even if cache capacity does not continue to increase, shortening the critical path can still bring gains.

Hybrid Bonding is a three-dimensional integration technology that directly bonds two wafers or dies. It does not rely on traditional microbump solder balls, but instead achieves electrical interconnection through direct copper-to-copper (Cu-Cu) contact and bonding of dielectric layers such as SiO₂. Compared with traditional packaging interconnects, hybrid bonding can shrink interconnect pitch from tens of micrometers to a few micrometers or even sub-micrometer levels, thereby providing thousands of times greater connection density per unit area.

This technology is crucial to logic folding: layers need a massive number of signal channels so that logic modules originally spread across a plane can still cooperate at high speed after being split across different layers. Huawei's statement that "the ratio of hybrid bonding pitch to top metal pitch is less than 3" is essentially measuring whether the interconnect density provided by bonding is sufficient to match the density of the chip's internal metal routing—the smaller the ratio, the less likely cross-layer connections are to become a bottleneck. Hybrid bonding was first mass-produced in CMOS image sensors, then used in memory products such as 3D NAND and HBM, and is now gradually moving toward high-performance logic chips.

How Chip Capabilities Reach the Phone Experience

The value of underlying technology ultimately depends on whether it can be translated into capabilities users can perceive. The changes in on-device AI and image processing in the Kirin 9050 series are the most direct examples of this.

A 30B Model Runs on a Phone

The difficulty of on-device large models is straightforward: memory is limited, and phones cannot sustain high power consumption for long periods. If all 30 billion parameters were stored at 4 bits, the weights alone would require about 15GB, which is clearly beyond what a phone can realistically handle.

The Kirin 9050 series' solution is multi-level compute-storage collaboration: loading the hot experts involved in computation into DDR, keeping experts not needed for the current computation in Flash, and combining this with low-bit quantization to reduce runtime memory requirements. After system-level optimization, the Kirin 9050 series can run a 30B MoE large model while adding less than 2.5GB of memory usage.

A scenario-adaptive approach also adjusts the scale of parameters involved in computation according to task complexity, letting the phone use its limited memory and power on more complex tasks. This supports a better local AI experience on the Mate 90 Pro Max, such as gallery organization—after the user expresses an intent, the phone can understand the request, break down the steps, and complete classification and album creation without connecting to the internet. This way of handling tasks is closer to the usage logic of a phone agent than simply adding another AI entry point.

MoE (Mixture of Experts) is a sparse-activation large model architecture. Unlike dense models that invoke all parameters for every inference, MoE splits the model into multiple "expert" subnetworks, and each input activates only a few of them, so the number of parameters actually involved in computation during inference is far smaller than the total.

This is exactly the key to running a 30B model on a phone: although the total weights require about 15GB, only a small portion of "hot experts" need to participate in computation at any given moment. Based on this, the Kirin 9050 series' multi-level compute-storage collaboration places hot experts in DDR and cold experts in Flash, while low-bit quantization compresses weight size, reducing runtime memory demand to less than 2.5GB of additional usage. The scenario-adaptive approach further determines how many experts to activate based on task complexity, allowing the phone to use less compute for simple tasks and call on more parameters only for complex ones, striking a balance among memory, power, and results.

Latency Control in the Imaging Pipeline

The AI ISP in the new Kirin 9050 series introduces a pixel-dedicated NPU inside the ISP and coordinates it with an external general-purpose NPU. As video algorithms increase, the original processing pipeline requires more module interaction, and latency becomes a constraint on image quality upgrades. The dual-engine architecture reduces queuing and interaction overhead through parallel processing.

According to the company, the related processing latency can be controlled within 16.7 milliseconds, which exactly matches the roughly 16.7-millisecond time budget for each frame of 4K 60fps video. This metric addresses whether high-image-quality processing can be completed in time, allowing algorithm upgrades to truly enter the continuous shooting experience.

AI ISP is an image processing unit that integrates neural network acceleration capabilities on top of a traditional image signal processor (ISP). A traditional ISP handles fixed-pipeline tasks such as demosaicing, noise reduction, white balance, and HDR composition, while an AI ISP can introduce neural networks into these stages to enable more complex algorithms such as AI noise reduction, semantic segmentation, portrait bokeh, and multi-frame fusion.

As video algorithms become increasingly complex, multiple modules inside the ISP need to interact repeatedly, and data queuing and scheduling overhead push up processing latency. Video is especially sensitive to latency: each frame of 4K 60fps video has only about a 16.7-millisecond processing budget, and once a frame processing times out, it leads to dropped frames or degraded image quality. The Kirin 9050 series introduces a pixel-dedicated NPU inside the ISP and coordinates it with an external general-purpose NPU to form a dual-engine architecture, reducing serial waiting through parallel processing. Keeping processing latency within 16.7 milliseconds means highly complex algorithms can stably enter the continuous shooting workflow, rather than being only a demo effect for a single photo.

Division of Labor in Display Calibration

The second-generation Linglong display on the Mate 90 series uses dual-layer OLED, but beyond high brightness, uniformity and color calibration at low brightness also require fine handling. Li Xiaolong, CTO of Huawei's Terminal BG, said that the display driver IC (DDIC) has limited storage space and struggles to hold more calibration data. Huawei's solution is to let the Kirin SoC participate in compensation: at high brightness it leverages the DDIC's power advantages, while scenarios requiring fine calibration such as low brightness are handled jointly by the SoC and the display chip.

Next-Generation Chips and the Engineering Problems That Cannot Be Avoided

When asked how many layers logic folding could eventually fold in the future, Xu Songyu did not give an upper limit. But he did reveal one key piece of information: the Kirin 2027 chip is already in Huawei's hands, and so far all test results have met expectations.

According to the available information, the evolution direction of Kirin logic-folding chips includes continued shrinking of hybrid bonding pitch, adding more interconnects, allowing more modules to participate in folding, and exploring more layers and optimized design tools.

The Number of Layers Is Not the Only Answer

Xu Songyu emphasized that the chip team and Huawei's phone team define things jointly, working backward from user experience goals to overall device metrics, and then determining chip specifications, architecture, and technical approaches. This explains why the evolution of logic folding cannot be simplified into continuously adding layers—phones need to make trade-offs among performance, power, and cost, and the value of new design space is to provide more options for achieving the goal.

The Real Constraints of Heat Dissipation and Yield

Logic folding also faces two engineering problems that cannot be avoided: heat dissipation and yield.

On heat dissipation, Xu Songyu emphasized that shortening communication distance and critical paths can reduce communication power consumption and improve overall energy efficiency, offering a way to reduce heat generation. But when it comes to temperatures under different workloads, local hotspots, and sustained performance, judgment still needs to be based on thermal design and test results.

On yield, Huawei will work with industry partners to improve it. In a review of the R&D process, Xu Songyu mentioned that in the early exploration stage there were gaps in tools, processes, and methods, and there was also uncertainty about whether performance and energy-efficiency gains could be achieved and whether high-yield mass production could be reached. Only as results at each stage met or even exceeded expectations did the team gradually build confidence.

He also made it clear that "no single company can answer all the questions alone." The barriers to logic folding run through design and manufacturing, and toolchains, cross-layer optimization, energy control, and testing all require sustained cooperation with industry partners.

The first Kirin logic-folding chip proved that this path can be taken. What Huawei needs to deliver next is to continuously translate the gains from cross-layer layout into products that can be mass-produced, are affordable, and are perceptible to users. The continued iteration of flagship phones will determine how far it can go.

One-line Summary

Huawei unveiled the first mass-produced logic-folding chip, the Kirin 9050 Pro, using 3D layered design and hybrid bonding to improve performance and power, with on-device AI and imaging gains.

Paragraph Summary

At its Terminal Innovation Technology Briefing, Huawei revealed details of the Kirin 9050 series, centered on the first mass-produced logic-folding chip, the Kirin 9050 Pro. The technology takes a 3D view, co-designing multiple dies as one chip, layering them by logical relationship and connecting them with dense vertical interconnects. Combined with more than 50 million hybrid bonds and a hybrid bonding pitch to top metal pitch ratio of less than 3, it shortens clock routing and critical paths and reduces clock distribution overhead. Compared with the Kirin 9030 Pro, CPU performance is up 25%, GPU performance is up 40% with power down 45%, and NPU compute is up 140% with power down 66%. On phones, this translates into running a 30B MoE large model with less than 2.5GB of added memory, keeping AI ISP processing latency within 16.7 milliseconds, and having the SoC participate in display compensation. The next-generation Kirin 2027 is already in testing with results meeting expectations, but heat dissipation and yield remain engineering challenges.