LOADBench: An Open-Source Dataset and Benchmark for Analog IC Design

Analog IC design has long relied on expert experience. Although machine learning methods have been widely expected to help, they have always been constrained by data silos and the lack of evaluation standards. Different papers use their own private datasets and custom metrics, making fair comparisons between methods difficult and greatly reducing the reproducibility of research results. LOADBench was created precisely to break this deadlock—it provides, in one go, a large-scale open-source dataset and standardized benchmark tasks.

The Dataset Covers More Than 100 Op-Amp Topologies

The core asset of LOADBench is an analog circuit dataset built on the SkyWater130 PDK. It includes more than 100 operational amplifier topologies, covering single-stage, two-stage, and three-stage structures. Each topology is not merely a netlist file, but comes with a complete set of engineering semantic information: structural and functional annotations, topology-specific sizing constraints (including symmetry and sizing rules), and a directly runnable Ngspice testbench.

More importantly, each topology is accompanied by the results of one multi-objective NSGA-II sizing optimization run, generating about 10³ Pareto-optimal solutions and 10⁶ intermediate sizing-performance pairs. This means researchers can study both the final optimal design points and the intermediate states during optimization, providing rich training signals for learning-based optimization algorithms.

SkyWater130 PDK is a 130nm process design kit (PDK) open-sourced by SkyWater Technology in collaboration with Google, and it is currently one of the most mainstream open-source chip fabrication processes. A PDK typically includes device models, layout rules, parasitic extraction scripts, and process corner parameters required for simulation, serving as the bridge between circuit design and actual tape-out. In LOADBench, choosing SkyWater130 means that every op-amp topology in the dataset is built on the same tape-out-capable, verifiable process premise, and the device models (such as the BSIM model for MOSFETs) and process parameters are fully public and stable. The benefits are twofold: on the one hand, researchers can reproduce all simulations without relying on a foundry's proprietary PDK; on the other hand, the sizing constraints and performance metrics of all topologies correspond to real physical design boundaries, giving the benchmark results industrial reference value rather than remaining merely at the level of idealized equations.

Ngspice is an open-source SPICE circuit simulator compatible with classic Berkeley SPICE syntax, supporting multiple analysis types such as DC, AC, transient, and noise. In LOADBench, each op-amp topology is equipped with a "directly runnable Ngspice testbench," that is, a prewritten set of netlists and simulation control statements that specify the excitation sources, load conditions, supply voltage, and performance metrics to be extracted (such as gain, bandwidth, phase margin, power consumption, etc.). Using Ngspice instead of commercial simulators ensures that anyone on any platform can reproduce the data generation process at zero cost, while also allowing automated scripts to batch-call simulations and batch-collect results, providing engineering feasibility for constructing 10⁶-scale sizing-performance pairs.

Six Standardized Benchmark Tasks

Data alone is not enough. LOADBench defines six tasks with precise evaluation protocols on top of the data: inverse sizing, topology selection, subcircuit classification, structured circuit generation, Pareto membership prediction, and multi-objective optimization.

These six tasks cover different stages of the analog design flow—from inferring sizing given performance, to selecting an appropriate structure from candidate topologies, to determining whether a design point lies on the Pareto front. Each task comes with clear input-output definitions and evaluation metrics, and reference implementations are released under open-source licenses, ensuring that different methods can be directly compared under the same conditions.

Inverse Sizing is a classic challenge in analog circuit automation: given target performance metrics (such as gain ≥ 80dB, unity-gain bandwidth ≥ 10MHz, power consumption ≤ 1mW), solve for the transistor sizes (W/L) and bias currents that satisfy these metrics. The problem is difficult because the mapping from sizing to performance is highly nonlinear, and multiple performance objectives often conflict with one another; conversely, the mapping from performance to sizing is even more one-to-many or many-to-many, with no analytical solution. LOADBench lists inverse sizing as an independent benchmark task precisely in the hope that machine learning models can learn this inverse mapping, thereby skipping the lengthy process of traditional iterative simulation and directly providing candidate sizing schemes. Evaluation metrics usually include the final performance compliance rate, simulation verification pass rate, and proximity to the true Pareto front.

Why This Matters

Analog IC design automation has a history of more than forty years, but the accumulation of open-source data lags far behind the digital circuit field. The metrics reported by different methods in papers are often incommensurable, making it difficult for reviewers and readers to judge whether a method represents genuine progress or merely performs well on a specific dataset.

By unifying the data format, testbenches, and metric definitions, LOADBench aligns the baseline for comparison. For researchers working on ML for EDA, it lowers the barrier to entering the analog design field; for industry, it provides a reproducible evaluation framework that helps identify methods with genuine deployment potential.

ML for EDA is a research direction formed at the intersection of machine learning and electronic design automation, aiming to use data-driven methods to accelerate or replace steps in traditional EDA flows that rely on expert experience and brute-force search. In the digital circuit field, there are already many public benchmarks (such as ISPD and ICCAD competition datasets) and mature flows, allowing researchers to compare the strengths and weaknesses of algorithms for tasks such as placement and routing and logic synthesis on a unified platform. In contrast, analog circuit EDA has long lacked similar infrastructure: design rules depend on the process, performance metric definitions vary widely, and simulation costs are high, making data difficult to share and methods difficult to compare. LOADBench fills precisely this gap—it transforms analog design tasks into clearly defined machine learning problems and provides data and evaluation protocols on a scale comparable to digital EDA benchmarks, enabling the focus of ML for EDA research to shift from "each creating its own data" to "comparing methods on the same track."

Open Licensing and Reproducibility

The dataset, annotation ground truth, and reference implementations of metric definition routines are all released under open licenses. This open strategy not only serves academic research, but also provides a legal and extensible starting point for industry to explore customized analog design flows.

LOADBench is not positioned as a leaderboard tool for any single method, but as infrastructure for the analog design automation community. When more and more methods report results on the same dataset and metrics, the field can truly accumulate comparable and inheritable knowledge.

One-line Summary

LOADBench releases a large-scale open-source op-amp dataset and six standard benchmarks, solving the data silo and incomparable evaluation problems in analog IC design.

Paragraph Summary

To address the long-standing problems of closed data and missing evaluation standards in analog IC design, LOADBench provides, in one go, a large-scale open-source dataset and standardized benchmark tasks. The dataset is built on the SkyWater130 PDK and covers more than 100 op-amp topologies. Each topology comes with structural/functional annotations, sizing constraints, an Ngspice testbench, and about 10³ Pareto-optimal solutions and 10⁶ intermediate sizing-performance pairs generated by one NSGA-II multi-objective optimization run. On top of the data, LOADBench defines six tasks with precise evaluation protocols: inverse sizing, topology selection, subcircuit classification, structured circuit generation, Pareto membership prediction, and multi-objective optimization. All resources are released under open licenses, with open-source reference implementations, ensuring that different methods can be directly compared under the same conditions. Its positioning is as infrastructure for the analog design automation community, promoting the accumulation of comparable and inheritable knowledge in the field.