The hard-core computation unit primitives of different FPGA vendors differ in primitive names, port naming, parameter configuration, and cascading methods, for example Xilinx's DSP48E2, Intel's DSP Block, and Lattice's sysDSP; the DSP48E2 has a three-stage structure of pre-adder, multiplier, and accumulator, and can be finely controlled through parameters such as INMODE, OPMODE, and ALUMODE.