Unverified50% confidenceFactExact time
WSE-3的片上SRAM容量达到44GB，SRAM访问延迟约1ns，比HBM约100ns低10-50倍
1
Sources
50%
Confidence
Long-term
Relevance
7/22/2026
First Seen
Sources
Related Claims
UnverifiedSRAM access latency is approximately 1 ns, HBM approximately 100 ns, making SRAM latency about 10–50 times lower than HBM.82% similarUnverifiedUnder a 45nm process, a single 32-bit floating-point multiplication consumes approximately 3.7pJ of energy, reading 32-bit data from off-chip DRAM consumes approximately 640pJ, and on-chip SRAM access requires approximately 5pJ.74% similarUnverifiedThe access latency of global memory (HBM or DDR) in Ascend AI processors is far higher than that of local SRAM, with the two potentially differing by tens to hundreds of times.71% similarUnverifiedThe WSE-3 is fabricated from a single 12-inch wafer, integrating approximately 4 trillion transistors, 900,000 AI-optimized cores, and 44 GB of on-chip SRAM memory.69% similarUnverifiedCompared to conventional GDDR6 memory, HBM can deliver 3–5 times higher memory bandwidth while consuming less power and occupying a smaller package footprint.69% similar
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