Unverified50% confidenceFactExact time
Blackwell's native hardware-level support for MX block-level scaling allows scaling factors to be fused with matrix multiplication operations during execution, which is the fundamental reason why FA4 MX8 performance numbers cannot be directly transferred to Hopper.
1
Sources
50%
Confidence
Long-term
Relevance
9/16/2026
First Seen
Sources
Related Entities
Related Claims
UnverifiedThe Blackwell architecture introduces fifth-generation Tensor Cores with native support for FP4×FP4 matrix multiply-accumulate operations, using FP32 or FP16 precision for the accumulator.68% similarUnverifiedNVIDIA's Blackwell architecture (B100/B200) natively supports matrix operations in MXFP4 format at the hardware level, with throughput nearly doubling compared to FP8.66% similarUnverifiedGPTQ is based on the OBQ framework, quantizing weights layer by layer and using the inverse of the Hessian matrix to compensate for quantization error, maintaining model quality even at 4-bit and even 3-bit precision.65% similarUnverifiedBlackwell is NVIDIA's next-generation microarchitecture following Hopper and Ada Lovelace, introducing fifth-generation Tensor Cores to improve FP4/FP6 inference efficiency.64% similarVerifiedNVIDIA designed a dedicated Tensor Core instruction mma.kind::mxf4 for NVFP4 in the Blackwell architecture (SM 100/103, such as the B100 and B200 series), and adopted an FP8 scaling factor mechanism with one scale per group of 16 elements.64% similar
Cite This Claim
Stable URI
https://kongchang.com/claim/927334API
curl https://kongchang.com/api/v1/knowledge/claims/927334MCP
get_claim(id=927334)