qwenGPU
An experimental project that compiles the parallel execution semantics of a 4-lane SIMT GPU into the weights of Qwen3.5-2B, using Gated DeltaNet states to serve simultaneously as registers and memory, and validating the feasibility of neural networks carrying hardware state machines.
Timeline (last 90 days)
The qwenGPU project compiles the GPU's parallel execution logic into Qwen3.5-2B, forming 45 untrained parameter layers.
qwenGPU uses the state of Gated DeltaNet to serve simultaneously as registers and memory.
qwenGPU maps the instruction stream, thread scheduling, and data paths of a 4-lane SIMT GPU.
qwenGPU claims that the model itself wrote out every step of a real CUDA launch.
The 45 layers of weights are untrained in their initial state.
qwenGPU follows the path of having a language model reproduce the evolution of a hardware state machine within its parameter space, rather than adding tool interfaces to the model to call CUDA.
Untrained means these layers have not yet undergone gradient optimization to fit real GPU behavior, and their actual execution fidelity still needs further verification.
All Facts (7)
The qwenGPU project compiles the GPU's parallel execution logic into Qwen3.5-2B, forming 45 untrained parameter layers.
50%UnverifiedqwenGPU uses the state of Gated DeltaNet to serve simultaneously as registers and memory.
50%UnverifiedqwenGPU maps the instruction stream, thread scheduling, and data paths of a 4-lane SIMT GPU.
50%UnverifiedqwenGPU claims that the model itself wrote out every step of a real CUDA launch.
50%UnverifiedThe 45 layers of weights are untrained in their initial state.
50%UnverifiedqwenGPU follows the path of having a language model reproduce the evolution of a hardware state machine within its parameter space, rather than adding tool interfaces to the model to call CUDA.
50%UnverifiedUntrained means these layers have not yet undergone gradient optimization to fit real GPU behavior, and their actual execution fidelity still needs further verification.
50%