Redwood
A dedicated AI accelerator designed for single-batch, low-latency inference scenarios, generated through automated AI system design. It is fabricated on Samsung 8nm process technology, supports an FPGA variant, and is capable of running large language models with billions of parameters.
Timeline (last 90 days)
The output of this fully automated AI pipeline is an AI accelerator called Redwood, specifically optimized for single-batch low-latency inference scenarios.
Projected data for Redwood on Samsung's 8nm process shows inference throughput 1.75× that of the measured Jetson Orin Nano.
Redwood reduces power consumption by 1.9× compared to the Jetson Orin Nano and improves performance per watt by 3.4× (based on projected data).
Redwood's FPGA variant is capable of running billion-parameter-scale Llama and Qwen models.
Each functional module of the system achieves 95% verification coverage through three methods: commercial EDA tools, a proprietary formal verification engine, and hardware-in-the-loop verification.
A single specification change takes only 48 hours from modification through re-verification to re-deployment on hardware.
Redwood's performance data is based on projected estimates rather than post-tapeout measurements.
Coverage encompasses multiple definitions such as code coverage, functional coverage, and branch coverage, with significant differences in value depending on the definition; the specific definition of the 95% coverage figure in this study is not clarified.
If the 48-hour closed-loop iteration is genuinely reliable, it would bring chip development close to the rapid iteration experience of the software domain.
All Facts (9)
The output of this fully automated AI pipeline is an AI accelerator called Redwood, specifically optimized for single-batch low-latency inference scenarios.
50%UnverifiedProjected data for Redwood on Samsung's 8nm process shows inference throughput 1.75× that of the measured Jetson Orin Nano.
50%UnverifiedRedwood reduces power consumption by 1.9× compared to the Jetson Orin Nano and improves performance per watt by 3.4× (based on projected data).
50%UnverifiedRedwood's FPGA variant is capable of running billion-parameter-scale Llama and Qwen models.
50%UnverifiedEach functional module of the system achieves 95% verification coverage through three methods: commercial EDA tools, a proprietary formal verification engine, and hardware-in-the-loop verification.
50%UnverifiedA single specification change takes only 48 hours from modification through re-verification to re-deployment on hardware.
50%UnverifiedRedwood's performance data is based on projected estimates rather than post-tapeout measurements.
50%UnverifiedCoverage encompasses multiple definitions such as code coverage, functional coverage, and branch coverage, with significant differences in value depending on the definition; the specific definition of the 95% coverage figure in this study is not clarified.
50%UnverifiedIf the 48-hour closed-loop iteration is genuinely reliable, it would bring chip development close to the rapid iteration experience of the software domain.
50%