#CPU-native LLM
2 related articles
·2 min
Training a CPU-Native LLM on Zero Budget: The Architectural Gamble of Ternary Quantization × Sparse MoE
An indie dev attempts to train a CPU-native LLM on $0 budget using ternary quantization, sparsity, and fine-grained MoE — with pre-registered success criteria and full public reporting.
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·3 min
CPU-Native Language Models: Breaking Through Inference Bottlenecks with Memory Bandwidth Co-Design
SiliconLLM builds a CPU-native LLM architecture from scratch, combining selective SSM, ternary (1.58-bit) LUT MLP, and granular MoE, co-designed around the L3 cache bandwidth cliff. Ternary kernels show 4-5x speedup over fp32.
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