AI Agents Design Chips at Higher Abstraction: HLS Workflow Achieves 2.6× Speedup

AI Agents for Chip Design: Moving from RTL to Higher-Level Abstraction

Large language model (LLM) agents are increasingly being integrated into chip design workflows, but most existing approaches operate directly at the register transfer level (RTL) — a low-level abstraction. A recent arXiv paper (arXiv:2609.21157) raises a thought-provoking question: if agents work at a higher level of abstraction, can they design better chips?

The answer is yes. By introducing High-Level Synthesis (HLS) as the agent's working layer — combined with RTL-level refinement — the research team achieved an average 2.6× geometric mean speedup over direct RTL design across a multi-task benchmark. This result offers a promising new path for agent-driven chip design.

A Four-Way Comparison of Design Approaches

To systematically evaluate how abstraction level affects agent design quality, the team designed and compared four distinct workflows:

Direct RTL Design

This is the approach most current LLM-based chip design agents use — the agent directly generates and modifies RTL code. The problem is that the abstraction level is too low: agents must manage an enormous amount of low-level detail, making it easy to lose track of the big picture in complex designs.

RTL (Register Transfer Level) is an abstraction layer in hardware design where designers explicitly specify data flow between registers, clock-edge-triggered logic operations, and combinational logic structures. Verilog and VHDL are the most common RTL description languages. RTL design demands deep understanding of timing, pipelining, resource reuse, and other low-level details. A moderately complex module can require hundreds or even thousands of lines of code, much of it structural boilerplate with no direct relation to functional logic. For LLM agents, this means maintaining a coherent sense of design intent in an extremely high-noise environment — even minor drift can introduce hard-to-debug timing violations or logic errors.

Agent-based HLS Design

This approach has agents work at the higher abstraction of HLS. HLS describes design intent in C-like high-level languages, which a compiler then automatically synthesizes into RTL. The research found that HLS "distills design knowledge into abstractions" that agents can leverage effectively, significantly reducing their cognitive burden.

High-Level Synthesis (HLS) allows designers to describe hardware behavior in high-level languages like C, C++, or SystemC. Synthesis tools (such as Xilinx Vitis HLS or Intel HLS Compiler) then automatically infer the corresponding RTL implementation, including pipeline scheduling, resource binding, and timing constraints. The key advantage of HLS is that designers can guide optimization through pragma directives (e.g., pipeline, unroll, dataflow) at a higher abstraction level, without manually wiring every register. This dramatically shortens design cycles while making code far easier for software-oriented tools or models to understand and generate. For LLM agents, C-style descriptions are semantically closer to their training data distribution, enabling more accurate mapping of functional requirements to valid, efficient hardware descriptions.

Post-Compiler HLS Refinement and Post-HLS RTL Refinement

The study also evaluated two refinement strategies: refining at the HLS level after compiler output (Post-Compiler HLS Refinement), and refining at the RTL level after HLS generates RTL (Post-HLS RTL Refinement). The latter is valuable because it can reclaim optimization opportunities that are only accessible at the lower level.

AHRR: Combining High-Level Abstraction with Low-Level Optimization

The paper's core contribution is combining "agent-based HLS design" with "post-HLS RTL refinement" into a complete workflow called AHRR (Agent-based HLS with RTL Refinement).

The design philosophy is clear: let the agent rapidly build a structurally sound, logically coherent design at the high-level abstraction, then drop back to RTL to reclaim low-level optimization headroom. In the team's own words, HLS "distills design knowledge into abstractions the agent can leverage," while RTL refinement "recovers low-level optimization opportunities." Together, they exploit the efficiency of high-level abstraction without sacrificing the precision of fine-grained tuning.

On a benchmark suite of 11 diverse tasks, AHRR achieved a 2.6× geometric mean speedup over direct RTL design — a result that clearly demonstrates the substantial impact of abstraction-level choice on agent-based chip design outcomes.

FPGA as Validation Platform and Generalizability of Findings

The team chose FPGA as their end-to-end evaluation platform due to its ease of deployment and rapid iteration, making it well-suited for full-workflow validation. However, the paper explicitly emphasizes that the design-flow tradeoffs they studied are largely target-process-agnostic — meaning AHRR's approach is not limited to FPGAs, and should transfer to ASIC and other chip implementation paths as well.

Case studies further support this conclusion: HLS abstraction helped agents better understand and organize designs, while RTL refinement compensated for the performance gaps inherent in purely high-level approaches. This layered "abstract first, refine later" strategy may well become a general paradigm for future agent-driven chip design.

FPGA (Field-Programmable Gate Array) is an integrated circuit whose internal logic structure can be reconfigured repeatedly after manufacture. Compared to one-time-fabrication ASICs, FPGAs have extremely low iteration costs, making them ideal as a validation vehicle for design methodology research. While FPGA resource primitives (LUTs, flip-flops, DSP blocks, BRAM) differ structurally from ASIC standard cells, the RTL design paradigm and HLS toolchains are highly consistent across both platforms. This means workflow optimization strategies validated on FPGAs carry the same core logic to ASIC design flows targeting TSMC, Samsung, and other process nodes — requiring only a swap of back-end synthesis and place-and-route tools. This is the technical basis for the paper's claim that its conclusions generalize across processes.

Implications for Agent-Driven Chip Design

The most important takeaway from this work may not be the specific 2.6× figure, but rather the directional insight it reveals: having AI agents work at the right level of abstraction is more effective than simply throwing more compute at them or forcing them to struggle with low-level code.

For teams exploring AI-assisted hardware design, this provides a reproducible reference framework. The research team has open-sourced their code and evaluation artifacts (GitHub: ZijD/AHRR), allowing interested developers to verify and extend the work.

As LLM agent capabilities continue to improve, designing the right "working abstraction" for them will become an increasingly critical challenge. AHRR's results demonstrate that the engineering choice of abstraction level is itself a fundamental component of agent system design.