DeepSeek Builds Its Own AI Chips: The Strategic Logic and Challenges Behind Compute Independence

DeepSeek's Chip Ambitions

Chinese AI company DeepSeek was recently reported to be planning to develop its own AI chips, a move that has drawn widespread industry attention. Founded in 2023 by quantitative hedge fund giant High-Flyer (Huanfang Technology), DeepSeek rose to prominence rapidly with its DeepSeek-V2, DeepSeek-V3, and the reasoning-focused DeepSeek-R1 series. Notably, as DeepSeek's parent company, High-Flyer's quantitative trading DNA has had a profound influence on DeepSeek's technical style. The core competitiveness of quantitative hedge funds lies in using mathematical models and algorithms to uncover subtle statistical patterns within massive datasets—a task that demands a strong engineering optimization mindset and meticulous management of computing resources. High-Flyer's deep learning infrastructure team has accumulated long-term experience operating large-scale GPU clusters, which forms an important foundation for DeepSeek's ability to break through on both algorithmic and engineering optimization fronts.

It is worth noting that the quantitative hedge fund industry and AI research share a deep methodological resonance in engineering culture: quantitative trading systems have long pursued maximizing computational throughput under microsecond-level latency constraints and strict capital limits—from low-latency hardware optimization in high-frequency trading, to vectorized parallel computing in statistical arbitrage models, to real-time stream processing in risk control systems. All these scenarios require engineers to treat every compute cycle with an almost "penny-pinching" attitude. This mindset of treating compute as a scarce resource and squeezing out its efficiency to the extreme aligns closely with DeepSeek's fine-grained management of FLOPs utilization, memory bandwidth, and communication overhead in model training. High-Flyer has long maintained self-built GPU clusters at the scale of tens of thousands of cards for high-frequency strategy backtesting, and its team's hands-on experience with GPU scheduling, CUDA kernel optimization, and distributed computing provides DeepSeek's engineering team with hardware operations expertise far exceeding that of typical AI startups.

Its core technical breakthroughs lie in the innovative combination of the Mixture-of-Experts (MoE) architecture and Multi-head Latent Attention (MLA), together with extreme engineering optimization.

Mixture-of-Experts (MoE) is a sparse computing paradigm that distributes model parameters across multiple "expert" sub-networks. Traditional dense models activate all parameters during each forward pass, whereas the MoE architecture uses a gating network routing mechanism to activate only a small number of expert modules—DeepSeek-V3 has 671B total parameters but activates only about 37B parameters per inference, dramatically reducing the floating-point operations (FLOPs) per computation. Multi-head Latent Attention (MLA) performs low-rank compression on the Key-Value cache, significantly reducing the KV Cache memory footprint during inference. This allows longer context windows or larger batch sizes under the same memory conditions, making it one of the key mechanisms behind DeepSeek's breakthrough compression of inference costs.

From a system design perspective, MoE's sparse activation and MLA's memory compression form an elegant functional complement: MoE addresses the "computation volume" problem—through sparse routing, each forward pass invokes only a small fraction of global parameters, keeping training and inference FLOPs within an affordable range; while MLA addresses the "memory bandwidth" bottleneck—in Transformer self-attention computation, the KV Cache memory footprint grows linearly with sequence length, forming the core constraint limiting long-context inference throughput. MLA projects the high-dimensional K and V matrices into a low-rank latent space (with compression ratios of 8-16x), greatly increasing the number of historical tokens that can be cached per unit of memory, thereby allowing larger batch sizes and amortizing fixed overhead. The net effect of these two mechanisms working in concert is precisely the engineering foundation that enabled DeepSeek-V3 to be trained using only about 2.78 million H800 GPU hours at a cost of roughly $5.5 million—far below Western models of comparable caliber.

As a Chinese company that has risen to prominence in the large-model field in recent years, DeepSeek has secured a place in the global AI race through its cost-effective model training strategy and open-source spirit. Now, it is setting its sights on the core of AI infrastructure—compute chips.

For a company known for model research and development, entering the chip domain is no accident. This move reflects the entire Chinese AI industry's urgent need for autonomous and controllable compute, and it is also a strategic choice by leading enterprises to actively pursue vertical integration against a backdrop of uncertainty in external supply chains.

Why DeepSeek Wants to Build Its Own Chips

The Practical Pressure of Compute Supply

Training and running inference on large models requires enormous compute resources. To understand this demand, one must first understand the architectural logic of AI chips: the core of modern AI chips is large-scale parallel computing units specifically optimized for matrix multiplication and vector operations. Unlike general-purpose CPUs, AI chips have thousands of streamlined compute cores paired with High Bandwidth Memory (HBM) to achieve ultra-high data throughput. NVIDIA's H100 uses HBM3 memory with bandwidth as high as 3.35TB/s, which is critical for the extensive memory access required by the attention mechanism in Transformer models. The compute precision (FP8/BF16/FP32) and memory hierarchy design in chip design directly affect model training efficiency, making them key dimensions requiring deep customization for in-house chips.

Currently, the global high-end AI chip market is almost monopolized by NVIDIA, whose H100, A100, and other GPUs are the primary tools for training frontier models. These chips have become the industrial standard for AI training thanks to their powerful parallel computing architecture—take the H100, for example: built on the Hopper architecture, a single card delivers nearly 2000 TFLOPS of FP16 compute and supports NVLink high-speed interconnect, making it a core component for building training clusters of tens of thousands of cards.

The importance of NVLink is especially pronounced in large-scale training scenarios. When training large models at the scale of hundreds of billions of parameters, model parameters must be distributed across hundreds or even thousands of GPUs, which need to frequently exchange gradients and activations. Traditional PCIe bus bandwidth is around 64GB/s (bidirectional), whereas NVLink 4.0 (used by the H100) offers bidirectional bandwidth as high as 900GB/s—a gap of more than 10x. This makes building NVLink-interconnected "island" clusters an engineering prerequisite for training ultra-large models. The H800 used by DeepSeek has reduced NVLink bandwidth compared to the H100, which prompted its team to make additional innovations in communication optimization algorithms to compensate for the hardware-level bandwidth gap.

However, due to factors such as export controls, Chinese enterprises' access to top-tier AI chips faces clear and continually tightening restrictions. Since 2022, the U.S. Department of Commerce has repeatedly expanded the scope of chip export controls against China, explicitly adding the H100, A100, and others to the restriction list, and applying dynamic controls through compute thresholds. Notably, these controls are not simply product-list controls but introduce technical thresholds based on compute metrics—using two indicators, "Total Processing Performance" (TPP) and "Performance Density," to build a two-dimensional control framework. TPP measures a chip's peak computing capability at INT8 precision, while performance density is TPP divided by chip area or power consumption, preventing companies from circumventing restrictions by stitching together multiple low-compute chips.

This approach of dynamic technical-metric control has profound policy design logic: it shifts the target of control from specific product models to abstract performance parameters, meaning that even if NVIDIA launches a "compliant version" chip specifically for the Chinese market, restrictions are automatically triggered as long as its performance exceeds the threshold. The choice of INT8 as the TPP benchmark is also significant—INT8 precision happens to be the mainstream precision for large-model inference deployment, rather than FP16 or BF16 commonly used in training, making the controls more precisely target the ability to deploy inference at scale. This dynamic technical-metric control approach makes it difficult for NVIDIA to simply bypass restrictions by lowering clock speeds or disabling some compute units, forcing Chinese customers to continually face a "performance ceiling" constraint. Chinese enterprises were forced to turn to NVIDIA's specifically downgraded H800 and A800, but these products were also brought under control in late 2023. This continually tightening policy environment fills Chinese AI enterprises' compute supply with uncertainty, serving as a direct institutional factor driving companies like DeepSeek to seek in-house chip development. Developing its own AI chips means being able to break away, to some extent, from dependence on a single supplier and holding the lifeline of compute in its own hands.

The Potential of Software-Hardware Co-Optimization

Beyond supply security, developing in-house chips also brings the possibility of deep software-hardware co-design. DeepSeek has unique accumulated expertise in model architecture and training methods. If it can customize chips tailored to the computational characteristics of its own models, it could theoretically achieve higher energy efficiency and lower cost per unit of compute. This "efficiency-first" philosophy has already been thoroughly validated at the model level, and extending it to the chip level has a natural consistency.

This "model-chip" integrated approach mirrors the logic behind Google's development of the TPU and Amazon's launch of the Trainium chip. Google officially released its first-generation Tensor Processing Unit (TPU) in 2016, whose core is the Systolic Array architecture—arranging a large number of simple multiply-accumulate (MAC) units in a two-dimensional grid, where data enters from the array edge and automatically flows between nodes to complete accumulation, without frequent memory write-backs. This architecture has a natural structural affinity with the core computation of Transformers: in attention computation, the multiplication of the query matrix Q with the key matrix K, as well as the weighted summation operation, can essentially be decomposed into regular matrix multiplications. The data flow pattern in the systolic array precisely matches the memory access pattern of such operations, minimizing off-chip memory access and achieving extremely high effective compute throughput at lower power.

A deeper reason is that the design goal of general-purpose GPUs is to "perform well across as many parallel computing scenarios as possible," and this generality itself implies a certain efficiency loss. Take MoE sparse routing computation in large-model training as an example: on a general-purpose GPU, when the gating network assigns different tokens to different experts, because the number of tokens received by each expert is uneven (the load-imbalance problem), some compute units idle and wait, reducing hardware utilization. A custom chip designed specifically for the MoE architecture, however, can embed a dynamic load-balancing scheduler at the hardware level, optimizing the dispatch and re-aggregation of tokens among physical compute units into a pipelined operation, fundamentally eliminating the compute-unit idling caused by sparse activation. This is precisely the core efficiency gain DeepSeek could achieve if it develops its own chip with a dedicated compute array customized for the MoE sparse activation pattern. Currently, TPUv4 already supports the training of large models such as Gemini; Amazon's Trainium focuses on low-cost, high-throughput training scenarios and is deeply integrated with PyTorch. The shared experience of both shows that when model scale and compute demand reach a certain magnitude, customized hardware can often surpass general-purpose GPUs in both performance and cost, forming a differentiated competitive advantage.

From Models to Chips: The Leap Is Not Easy

Although the strategic direction is clear, transitioning from a model company to a chip designer faces enormous technical barriers and practical challenges.

The High Investment and Long Cycle of Chip Development

Chip design is a capital-intensive, talent-intensive, and long-cycle systems engineering endeavor. From architecture design and tape-out verification to mass production, it typically requires several years and sustained investment on the order of billions of dollars. Even if the design phase is completed smoothly, there remains the bottleneck of advanced-process foundry capacity—a manufacturing-side predicament with deep technical roots.

Advanced-process chip manufacturing is highly dependent on the Extreme Ultraviolet lithography machines (EUV) produced by ASML of the Netherlands. EUV uses extreme ultraviolet light with a wavelength of 13.5nm as the exposure light source. Compared to the previous generation of Deep Ultraviolet lithography (DUV, 193nm), it can achieve finer pattern transfer in a single exposure, making it a necessary means for mass-producing processes below 7nm. ASML is the world's only manufacturer of EUV lithography machines, with each unit valued at around $200 million, and its technical barriers are physically largely irreplicable—the equipment has been fully restricted from export to China since 2019. Without EUV lithography machines, mass-producing processes below 7nm is virtually impossible.

The "Multi-Patterning" technology currently used by SMIC is a workaround: splitting a pattern originally completed in a single exposure into multiple superimposed DUV exposures, which can theoretically approach 7nm results. However, the yield challenge of this approach stems from the cumulative effect of "overlay error." Every lithography exposure step has nanometer-level alignment deviations, with typical alignment precision of about 1-2nm per exposure. When 4-8 exposure overlays are required, the random deviations of each exposure accumulate in an approximately root-mean-square manner, causing the final pattern's deviation from the design target to grow significantly, thereby triggering defects such as transistor characteristic drift and connection breaks. In addition, each additional lithography step means extra photoresist coating, exposure, development, and etching processes, doubling the total number of process steps and causing overall yield to decline exponentially.

Here lies an engineering-economics paradox worth noting: multi-patterning technology is not incapable of producing advanced chips—rather, the "production cost" is too high. Huawei's Kirin 9000S chip has already proven that SMIC can mass-produce a complex SoC using the N+2 process (essentially an optimized 7nm multi-patterning solution). But the demand characteristics of AI training chips are entirely different from those of phone SoCs: the former requires bulk shipments of tens of thousands or even hundreds of thousands of highly consistent chips, and any slight decline in yield gets sharply amplified under scale effects, causing effective capacity to fall far below nominal capacity. This is precisely why, even with multi-patterning technology in hand, SMIC's mass production cost remains 3-5x that of TSMC at the same node, while still lagging in transistor density and power performance. High-end AI chips rely on advanced processes below 7nm, and the eligibility of overseas foundries like TSMC to accept orders also faces policy risks. This structural constraint on the manufacturing side is the biggest practical challenge that DeepSeek's chip plan must confront, and it is also a shared predicament long faced by the entire Chinese AI chip industry—including pioneers such as Huawei Ascend, Cambricon, and Biren Technology.

Building the Ecosystem and Software Stack

NVIDIA is hard to shake largely thanks to the deep moat built by its CUDA ecosystem. CUDA (Compute Unified Device Architecture) is the parallel computing platform and programming model launched by NVIDIA in 2007. After nearly two decades of accumulation, it has formed a complete software stack encompassing cuDNN (deep neural network acceleration library), cuBLAS (linear algebra library), NCCL (multi-GPU communication library), and TensorRT (inference optimization engine). The underlying operators of mainstream frameworks like PyTorch and TensorFlow are all deeply dependent on this ecosystem.

The true barrier of the CUDA ecosystem lies in the superposition of time accumulation and network effects, and this barrier reaches down to the hardware microarchitecture level. Take cuDNN as an example: it maintains dozens of different implementation algorithms for convolution operations (such as Winograd convolution, FFT convolution, direct convolution, etc.) and automatically selects the optimal implementation based on the shape of the input tensor, the data type, and the hardware generation. These implementations internally use extensive assembly-level optimizations targeting specific NVIDIA hardware generations—for example, leveraging the asynchronous memory copy instructions (cp.async) of the Ampere architecture to pipeline compute and data loading, as well as precise Tensor Core invocation, warp-level primitive operations, and shared-memory bank-conflict avoidance. For competitors, replicating such optimizations requires not only understanding the algorithms themselves but also deeply mastering the microarchitectural details of the target hardware—the latter usually being a chipmaker's most core trade secret.

This microarchitecture-level lock-in manifests in actual engineering as an "asymmetric optimization gap": even if a competitor's chip matches NVIDIA in theoretical peak compute, in actual large-model training it can often only achieve 60-80% of theoretical efficiency, whereas NVIDIA GPUs, backed by CUDA, can reach 85-95% of theoretical efficiency. The fundamental cause of this gap is precisely the hundreds of thousands of battle-tested hardware microarchitecture-level optimizations, which are deposited across the millions of lines of code in libraries like cuDNN and cuBLAS—optimizations that any competitor would need years to match one by one. Since its release in 2007, millions of developers worldwide have accumulated vast amounts of optimized code and debugging experience on CUDA; AI courses at major universities default to CUDA as the programming environment; and the underlying implementations of thousands of open-source projects are deeply bound to the CUDA API. This ecosystem lock-in effect means that even if a competitor launches hardware of comparable performance, the migration cost remains extremely high.

For new entrants, building a substitutable software stack means re-implementing high-performance versions of thousands of operators, developing compilers that support automatic differentiation and graph optimization, and securing official adaptation from mainstream frameworks. Huawei Ascend's CANN and Cambricon's CNToolkit have been on this path for many years and still face challenges in operator coverage and performance alignment, profoundly revealing the true thickness of software ecosystem barriers. For DeepSeek's in-house chips to truly deliver value, it must simultaneously build a supporting software ecosystem—an extremely complex systematic undertaking that cannot possibly be completed in the short term.

The Vertical Integration Trend in China's AI Industry

DeepSeek's chip plan is not an isolated case but a microcosm of the Chinese AI industry's overall move toward autonomy and self-control. In recent years, more and more tech companies have begun ramping up investment in compute infrastructure, attempting to build a complete, autonomous technology stack spanning chips, frameworks, and models. China has formed a group of AI chip companies with some competitiveness: HiSilicon's Huawei Ascend 910B has achieved fairly large-scale adoption in the domestic large-model training market; Baidu's Kunlunxin focuses on inference scenarios; Cambricon's MLU series is deeply invested in data center acceleration; and emerging companies such as Enflame and Biren Technology are also continuously catching up. Although these companies still lag NVIDIA's flagship products by a generation on key metrics such as absolute compute value, interconnect bandwidth, and software ecosystem maturity, the overall ecosystem is accelerating its growth.

This vertical integration trend is, on one hand, the result of external pressure, and on the other hand, reflects the inherent logic of an industry reaching a certain stage of maturity: when AI becomes a core competency, mastering the underlying compute means holding the initiative in development.

What is worth noting is that DeepSeek was previously renowned for its open-source route and low-cost training strategy. If its in-house chips can continue this cost-effective design philosophy, it may provide the entire industry with a brand-new paradigm distinct from "infinitely piling up compute"—achieving higher efficiency under more constrained hardware conditions through software-hardware co-optimization is precisely the methodology DeepSeek has already proven at the model level.

Conclusion: Worth Watching, But Still Wait and See

Currently, public information about DeepSeek's chip plan remains quite limited; the specific technical roadmap, launch timeline, and partners are all yet to be clarified. This is more of a signal releasing strategic intent, and there is still a considerable road ahead before an actual product materializes.

However, the news itself is already telling enough: the main battlefield of AI competition is extending from the model level down to the underlying compute, and leading enterprises are accelerating the construction of deeper technical barriers. For DeepSeek, whether it can successfully clear this high bar of AI chip development—not just chip design itself, but also supply chain assurance on the manufacturing side and building a software ecosystem from scratch—will largely determine its future strategic position in the global AI landscape. We may as well keep watching and await the disclosure of more details.

Key Takeaways

Key Takeaways