RTL-Interact: Teaching LLMs to Design Chips by Interacting with EDA Tools

Large language models are making inroads into chip design, but to truly produce usable RTL code, a single generation pass is far from enough—designers need to repeatedly check, locate problems, and revise using EDA tools. Most existing RTL-specific models lack the ability to learn interaction with EDA tools, or they split generation and repair into two separate modules, resulting in a fragmented and inefficient workflow. RTL-Interact is proposed precisely to train a single model that can autonomously complete the "generate—check—revise" loop.

From Generation to Closed Loop: The Core Idea of RTL-Interact

RTL-Interact is a multi-task post-training framework aimed at enabling a single RTL-specific model to master three capabilities simultaneously: generating RTL implementations, constructing task-matched EDA checks, and revising code based on tool feedback.

The key to this design is treating "interaction" itself as a learnable skill, rather than stitching together external scripts at inference time. Through automatically constructed multi-task demonstration data and staged supervision from chain-of-thought to tool-integrated reasoning, the framework enables the model to gradually learn when to invoke checks, how to interpret feedback, and how to make targeted modifications.

Compared to approaches that rely on separate generators and repairers, having a single model complete the entire workflow reduces information loss between modules and allows the model to directly perceive during training how EDA feedback affects final correctness.

RTL (Register Transfer Level) is an abstraction level in digital chip design that describes data transfer between registers and combinational logic, typically written in hardware description languages such as Verilog, SystemVerilog, or VHDL. Unlike software code, syntactic correctness in RTL code does not imply functional correctness: the same module may compile successfully yet fail on timing, reset, or boundary conditions. Therefore, RTL design must rely on EDA (Electronic Design Automation) tools for verification; typical steps include simulation (e.g., VCS, ModelSim to check functional behavior), synthesis (e.g., Design Compiler to determine synthesizability), and formal verification. These tools return error messages, warnings, and logs, which designers use to locate and fix code. Understanding this "write—verify—fix" cycle between RTL and EDA tools is the prerequisite for grasping why RTL-Interact emphasizes closed-loop interaction.

PAPO: A Reward Mechanism Designed for Multi-Task Reinforcement Learning

After supervised learning, the research team introduced Pattern-Aware Policy Optimization (PAPO) for multi-task reinforcement learning. PAPO makes two modifications on top of Group Relative Policy Optimization.

First, it adds a correctness-gated reward: rewards are granted only when checks succeed and the process is concise, while effective revisions are also positively incentivized. This means the model cannot "get lucky" by piling on large numbers of tool calls; it must control checking costs while ensuring correctness.

Second, task grouping is used to maintain coverage across objectives, preventing the model from favoring one type of task during reinforcement learning at the expense of others. In multi-task settings, this grouping mechanism is particularly important for maintaining overall performance.

GRPO (Group Relative Policy Optimization) is a reinforcement learning algorithm that requires no separate value network: it samples a group of responses for the same prompt and uses the relative rewards within the group as advantage estimates, thereby eliminating the critic model and reducing training overhead. PAPO retains this intra-group comparison framework but adapts the reward design for RTL multi-task scenarios—using "correctness gating" to filter out samples that fail checks or have redundant processes, and task grouping to ensure that different tasks such as generation, check construction, and revision are all covered in sampling batches, preventing policy degradation onto a single task.

Benchmark Performance: Surpassing the Teacher Model

According to the paper's data, on the CVDP benchmark, RTL-Interact-32B achieves 48.7% weighted Pass@1 and 68.9% Pass@5, surpassing its teacher model DeepSeek^Ad-V3.2; RTL-Interact-8B also reaches 44.9% weighted Pass@1.

More notable are the efficiency results: PAPO can improve Pass@1 while reducing average tool calls by 63.8%. This directly addresses a real pain point in RTL interaction—EDA tool calls are often time-consuming and expensive, so reducing unnecessary checks has clear significance for practical design workflows.

Both models also outperform all RTL-specific baselines on VerilogEval v2 and RTLLM v2, indicating that the benefits of this approach are not limited to a single benchmark.

Pass@k is a commonly used evaluation metric in code generation: for the same problem, k candidate solutions are sampled, and success is counted if at least one of them passes all tests; unbiased estimates are typically reported. Weighted Pass@1 weights Pass@1 by problem difficulty or category to prevent easy problems from dominating the overall score. CVDP (Comprehensive Verilog Design Problems) is a benchmark for RTL generation covering tasks ranging from module implementation to debugging and repair; VerilogEval v2 and RTLLM v2 are also mainstream evaluation sets for RTL code generation, focusing on different difficulty levels and problem types. Only by considering these benchmarks together can one judge whether the method's benefits are general rather than tailored to a single dataset.

Why This Direction Is Worth Watching

Chip design demands extremely high correctness; passing syntax checks in RTL code does not equal functional correctness, and real verification depends on EDA steps such as simulation and synthesis. Teaching models to "verify themselves with tools" is closer to engineering reality than simply scaling up code generation.

The value of RTL-Interact lies in incorporating tool feedback into the training objective and using reinforcement learning to explicitly optimize the balance between "checking cost" and "revision effectiveness." This approach also has reference value for other code generation scenarios that require external tool verification—models should not just write code but also learn to verify and correct errors.

Of course, the stability of multi-task reinforcement learning and generalization across toolchains remain issues that require continued observation before such methods can become practical.

One-line Summary

RTL-Interact uses multi-task post-training and PAPO reinforcement learning to enable a single model to complete the RTL generation, EDA checking, and revision loop.

Paragraph Summary

RTL-Interact is a multi-task post-training framework for chip design that aims to enable a single RTL-specific model to simultaneously master three capabilities: generating RTL implementations, constructing task-matched EDA checks, and revising code based on tool feedback, thereby forming a "generate—check—revise" loop and avoiding the workflow fragmentation caused by separating generators and repairers. The framework first uses automatically constructed multi-task demonstration data for staged supervision, then introduces Pattern-Aware Policy Optimization (PAPO) for multi-task reinforcement learning: building on GRPO, it adds correctness-gated rewards and task grouping, both suppressing the behavior of gambling by piling on tool calls and maintaining coverage of each task capability. On CVDP, RTL-Interact-32B achieves 48.7% weighted Pass@1 and 68.9% Pass@5, surpassing the teacher model DeepSeek-V3.2; PAPO also reduces average tool calls by 63.8%, and both models outperform RTL-specific baselines on VerilogEval v2 and RTLLM v2.