Unverified50% confidenceFactExact time
According to a Bilibili video, Changxin Memory successfully developed a 4F2 memory architecture, reducing the single-cell area by about 30% and raising the capacity ceiling of domestic HBM.
1
Sources
50%
Confidence
Medium-term (~90 days)
Relevance
10/21/2026
First Seen
Valid until: 1/19/2027
Sources
Related Entities
Related Claims
UnverifiedHBM4 is planned to increase the number of stacked layers to 16–20, achieving approximately 4 TB of capacity per square centimeter, but each layer receives only about 20% of the single-chip bandwidth.73% similarUnverified4F² is a measure of area efficiency for DRAM memory chips, meaning each memory cell occupies only 4 times the minimum feature size in area, representing the theoretical limit of storage density, while mainstream DRAM today typically ranges between 6F² and 8F².72% similarVerified4-bit量化使模型存储空间缩减为FP16的约1/472% similarUnverified一张1024×1024的未压缩RGBA纹理占据4MB存储空间71% similar
Cite This Claim
Stable URI
https://kongchang.com/claim/1082541API
curl https://kongchang.com/api/v1/knowledge/claims/1082541MCP
get_claim(id=1082541)