BenchmarkComprehensive Verilog Design Problems

CVDP

CVDP is a benchmark for RTL generation whose problems cover a variety of tasks from module implementation to debugging and repair, used to evaluate the ability of large models to generate and repair hardware description language code.

Timeline (last 90 days)

Nov 2

According to the paper's data, on the CVDP benchmark, RTL-Interact-32B achieves 48.7% weighted Pass@1 and 68.9% Pass@5, surpassing its teacher model DeepSeek-V3.2.

Unverified50%

Nov 2

CVDP (Comprehensive Verilog Design Problems) is a benchmark for RTL generation whose problems cover a variety of tasks ranging from module implementation to debugging and repair.

Unverified50%

All Facts (2)

Unverified

According to the paper's data, on the CVDP benchmark, RTL-Interact-32B achieves 48.7% weighted Pass@1 and 68.9% Pass@5, surpassing its teacher model DeepSeek-V3.2.

50%Unverified

CVDP (Comprehensive Verilog Design Problems) is a benchmark for RTL generation whose problems cover a variety of tasks ranging from module implementation to debugging and repair.

50%

Source Articles

RTL-Interact: Teaching LLMs to Design Chips by Interacting with EDA ToolsNov 2