ERC
Electrical Rule Check, used to verify electrical connection issues at the PCB schematic level, such as power, ground, and floating pins.
Timeline (last 90 days)
The model autonomously ran ERC (Electrical Rules Check) and DRC (Design Rules Check), and modified the circuit and layout based on the check results, forming a self-iterating loop of design–check–correction
ERC is responsible for checking logical errors at the schematic level (such as unconnected pins, signal short circuits, and power network conflicts), while DRC verifies physical constraints at the PCB level (such as trace spacing, via annular ring width, and copper overlap)
KiHub supports schematic and PCB visual version comparison, precise comments with positioning, automated checks (including DRC, ERC, and BOM consistency checks), and approval workflow management.
All Facts (3)
The model autonomously ran ERC (Electrical Rules Check) and DRC (Design Rules Check), and modified the circuit and layout based on the check results, forming a self-iterating loop of design–check–correction
50%UnverifiedERC is responsible for checking logical errors at the schematic level (such as unconnected pins, signal short circuits, and power network conflicts), while DRC verifies physical constraints at the PCB level (such as trace spacing, via annular ring width, and copper overlap)
50%UnverifiedKiHub supports schematic and PCB visual version comparison, precise comments with positioning, automated checks (including DRC, ERC, and BOM consistency checks), and approval workflow management.
50%