Logic Folding
An evolutionary approach in advanced process nodes and chip design that, through coordinated optimization of transistor structures, metal interconnects and packaging methods, continues to compress the area and energy consumption of logic units beyond a single process node, emphasizing joint innovation across design, process and packaging.
Timeline (last 90 days)
Traditional chip design unfolds on a two-dimensional plane, requiring data to travel a relatively long path; the Kirin 9050 Pro designs multiple dies cooperatively as a single complete chip, laying them out in layers according to logical relationships and connecting layer to layer with dense vertical interconnects.
The evolution directions of the Kirin logic-folding chip include continuing to shrink the hybrid bonding pitch, adding interconnects, having more modules participate in folding, and exploring more layers and optimizing design tools.
Logic folding faces two unavoidable engineering problems, heat dissipation and yield, and Huawei will work with industry partners to improve yield, with Xu Songyu stating that no single company can answer all the answers alone.
All Facts (3)
Traditional chip design unfolds on a two-dimensional plane, requiring data to travel a relatively long path; the Kirin 9050 Pro designs multiple dies cooperatively as a single complete chip, laying them out in layers according to logical relationships and connecting layer to layer with dense vertical interconnects.
50%UnverifiedLogic folding faces two unavoidable engineering problems, heat dissipation and yield, and Huawei will work with industry partners to improve yield, with Xu Songyu stating that no single company can answer all the answers alone.
50%UnverifiedThe evolution directions of the Kirin logic-folding chip include continuing to shrink the hybrid bonding pitch, adding interconnects, having more modules participate in folding, and exploring more layers and optimizing design tools.
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