ConceptTSMC N2P
N2P
A performance-enhanced variant in TSMC's 2-nanometer family, a derivative process following the N2 node. It further optimizes the gate-all-around (GAA) nanosheet transistors introduced in N2, typically offering performance or energy-efficiency gains ranging from a few percentage points to about ten percent.
Timeline (last 90 days)
Oct 14
Maia 300 is equipped with 8 HBM4 memory stacks, uses compute chiplets manufactured on TSMC's N2P process, and is deployed in the form of 96-accelerator racks.
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