PCBEditor
An AI-assisted PCB design tool that converts natural language descriptions into fully laid-out, routed circuit boards that pass design rule checks and include standard manufacturing files. It incorporates a built-in autorouter named Sadie, written in Rust.
Timeline (last 90 days)
PCBEditor can convert a natural-language description into a PCB that is fully laid out, routed, has passed design rule checks, and includes standard manufacturing files.
PCBEditor divides its work into two categories: judgment tasks (component selection, topology, and netlist drafting) are handled by the language model, while measurement tasks (layout, routing, design rule checking, and export) are handled by a deterministic engine.
The PCBEditor system is model-agnostic, runs on a hosted API, currently uses AWS Bedrock, and has not fine-tuned any model.
PCBEditor's routing is performed by a Rust-based autorouter named Sadie, which uses multi-layer A* algorithm, rip-up and reroute, Hammerstad–Jensen impedance modeling, and graph-based connectivity proof.
The language model stage may return different drafts across different runs, but the layout stage is deterministic: the same netlist combined with the same rules will always produce the same board.
PCBEditor outputs standard manufacturing data: Gerber (RS-274X), Excellon drill files, pick-and-place coordinates, BOM, and a native KiCad .kicad_pcb file.
When a board cannot be fully routed, PCBEditor does not report a completion percentage but instead directly lists the specific net names that could not be completed.
Dense fine-pitch BGAs are the most difficult cases for PCBEditor to handle, requiring fanout routing before the general-purpose router can take over, and are the most likely place for unrouted nets to appear.
PCBEditor is not a signal integrity suite, and demanding high-speed or RF designs still require dedicated signal integrity analysis.
PCBEditor's component library is smaller than that of established desktop tools, and for uncommon components the pad layout needs to be verified against the datasheet.
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All Facts (15)
PCBEditor can convert a natural-language description into a PCB that is fully laid out, routed, has passed design rule checks, and includes standard manufacturing files.
50%UnverifiedPCBEditor divides its work into two categories: judgment tasks (component selection, topology, and netlist drafting) are handled by the language model, while measurement tasks (layout, routing, design rule checking, and export) are handled by a deterministic engine.
50%UnverifiedThe PCBEditor system is model-agnostic, runs on a hosted API, currently uses AWS Bedrock, and has not fine-tuned any model.
50%UnverifiedPCBEditor's routing is performed by a Rust-based autorouter named Sadie, which uses multi-layer A* algorithm, rip-up and reroute, Hammerstad–Jensen impedance modeling, and graph-based connectivity proof.
50%UnverifiedThe language model stage may return different drafts across different runs, but the layout stage is deterministic: the same netlist combined with the same rules will always produce the same board.
50%UnverifiedPCBEditor outputs standard manufacturing data: Gerber (RS-274X), Excellon drill files, pick-and-place coordinates, BOM, and a native KiCad .kicad_pcb file.
50%UnverifiedWhen a board cannot be fully routed, PCBEditor does not report a completion percentage but instead directly lists the specific net names that could not be completed.
50%UnverifiedDense fine-pitch BGAs are the most difficult cases for PCBEditor to handle, requiring fanout routing before the general-purpose router can take over, and are the most likely place for unrouted nets to appear.
50%UnverifiedPCBEditor is not a signal integrity suite, and demanding high-speed or RF designs still require dedicated signal integrity analysis.
50%UnverifiedPCBEditor's component library is smaller than that of established desktop tools, and for uncommon components the pad layout needs to be verified against the datasheet.
50%UnverifiedWhen reviewing an AI-designed PCB, attention should be focused on the model's decisions (component selection and connectivity), as these types of errors can pass all geometric checks while appearing reasonable.
50%UnverifiedOnce a schematic has been reviewed and confirmed, it should be saved and used as the basis for further work, as regenerating with the same prompt will produce a new draft that requires re-review.
50%UnverifiedResults that can only be verified within a vendor's own tools are equivalent to no verification; open-standard outputs return verification control to the user, allowing design rule checks to be run in KiCad using fab-house rules.
50%UnverifiedPCBEditor targets prototyping, learning, and small-to-medium board design, and is especially suited for environments without desktop CAD; it is not a replacement for professional EDA suites or engineering review.
50%UnverifiedPCBEditor's designs are processed on its servers, prompts and design intent are sent to a hosted model provider as part of the generation process, and footprint and symbol data come from the KiCad library licensed under CC-BY-SA-4.0.
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