Can You Trust an AI-Designed PCB? A Seven-Point Checklist Before You Order

AI tools can hand you a fully laid-out, routed, design-rule-checked board in minutes. The useful question isn't "does it look right?" — it's "which parts were decided by a language model, and which were calculated by a deterministic engine?" These two types of output fail in completely different ways and require completely different verification strategies.

This article is based on PCBEditor's system card. PCBEditor converts a natural-language description into a PCB with completed layout, routing, design rule checks, and standard manufacturing files. Understanding how it divides responsibility between the model and the computational engine determines exactly what you should focus on before sending your board to fab.

Understand Which Decisions Come From the Language Model

PCBEditor explicitly splits its work into two categories — and this distinction is the key to understanding the tool's overall trustworthiness.

Judgment calls — handled by the language model: component selection, proposing topology, and drafting the netlist. This is fundamentally reasoning over accumulated design knowledge, which is exactly what language models are good at. The system itself is model-agnostic, running on a hosted API (currently AWS Bedrock) with no fine-tuning applied.

Measurements — handled by deterministic engines: placement, multi-layer routing, design rule checking, and export. A language model cannot measure whether a trace is 0.15 mm from a pad, so the system never asks it to. Routing is handled by a Rust-based autorouter called Sadie, which uses multi-layer A*, rip-up and reroute, Hammerstad–Jensen impedance modeling, and graph-based connectivity proofs.

What this division means for your review: focus your attention on the model's decisions — component selection and connectivity. Errors here look completely reasonable on screen. A wrong pin assignment or a missing pull-up resistor will pass every geometric check. The geometric side is computed and should be verified with tools, not by eye.

Sadie's A* algorithm is a classic shortest-path method on a graph that uses a heuristic function to estimate remaining cost, efficiently planning trace paths across a copper grid. Rip-up and reroute means that when a trace can't complete in the current state, the autorouter actively undoes adjacent already-routed traces to free space and tries again — the standard way autorouters break through congestion. Hammerstad–Jensen impedance modeling is an empirical transmission-line formula that calculates the characteristic impedance of microstrip or stripline traces from width, copper thickness, and dielectric parameters, ensuring controlled-impedance nets (such as USB and high-speed differential pairs) meet their target impedance. What all these algorithms share: given the same inputs, the output is fully deterministic — a sharp contrast to the probabilistic reasoning of a language model, and the technical foundation for the "judgment vs. measurement" division this article emphasizes.

Same Netlist, Same Board

The model stage may return a different draft on different runs — and even more so across model versions. The layout stage will not: the same netlist plus the same rules always produces the same board. That means the review you did yesterday still describes the same board today, even if the model behind the first stage has been updated.

The practical takeaway is straightforward: once you've reviewed and confirmed a schematic, save it and build from it. Running the same prompt again produces a new draft, and a new draft requires a new review.

Verify the Board Outside the Tool

PCBEditor outputs standard manufacturing data: Gerber (RS-274X), Excellon drill files, pick-and-place coordinates, BOM, and a native KiCad .kicad_pcb file. This means you can verify it with software you trust.

Specifically: open the .kicad_pcb file in KiCad and run a design rule check using your fab's rules. Load the Gerber and drill files into a Gerber viewer and inspect copper, board outline, and hole positions layer by layer.

One principle to keep in mind: a result that can only be verified inside the vendor's own tool is not verified. This is the core value of open-standard output — it puts review authority back in your hands.

Gerber (RS-274X) is the universal vector format for PCB manufacturing. Each file corresponds to one layer — copper, silkscreen, or solder mask — and describes all the contours and aperture flashes on that layer. Excellon format is dedicated to drill information, containing the coordinates, diameter, and type (through-hole or blind) of every hole. Both formats have decades of industrial validation; virtually every PCB fab and automated optical inspection system can read them directly. Loading them into an independent Gerber viewer (such as gerbv or the online viewers provided by major fabs) for layer-by-layer visual inspection is a verification step completely decoupled from the generation tool. Even if PCBEditor has any rendering discrepancies internally, the Gerber files represent what the manufacturing equipment will actually produce. Any layer misalignment, missing copper, or hole position anomaly will surface at this step.

Look at the Unrouted Net List, Not a Percentage

When a board can't be fully routed, PCBEditor doesn't report a "completion percentage" — it lists the specific net names it couldn't complete. A number like "94% routed" hides which connections are missing; a list of net names tells you exactly where to look.

Most unrouted net issues are actually placement issues. The fix is to move the components at both ends of the named nets, give congested areas more breathing room, and re-route.

Know Where It's Weakest

The tool's boundaries matter just as much as its capabilities. A few known weak points worth planning around:

Dense fine-pitch BGAs are the hardest case. They require escape routing before a general-purpose router can take over, and this is where unrouted nets are most likely to appear. For these components, plan for more layers or use via-in-pad.

It is not a signal integrity suite. Controlled-impedance nets are handled during routing, but demanding high-speed or RF designs still require dedicated signal integrity analysis.

AI output is a first draft. The reliable workflow is AI drafts, human reviews — confirm the schematic before it becomes copper.

The component library is smaller than mature desktop tools. For less common parts, check every footprint against the pad diagram in the datasheet.

BGA (Ball Grid Array) is a package type where solder balls are densely arranged on the chip's underside, typically at 0.5 mm to 1 mm pitch. Balls in the center area cannot be routed directly from the chip edge. Escape routing refers to bringing those inner balls out through vias to other routing layers so a general-purpose router can handle the remaining connections. This step has strict requirements for via size, layer spacing, and via placement, which general autorouters struggle to handle independently — the fundamental reason BGA packages are the most common source of unrouted nets in automated flows. Via-in-pad places vias directly within the pad footprint, significantly shortening escape paths and saving routing space, but requires filled and plated vias from the fab, which adds cost. Confirm this process capability with your fab before ordering.

Use It in the Right Context

PCBEditor is aimed at prototyping, learning, and small-to-medium board designs — especially in environments without desktop CAD available, such as Chromebooks, tablets, or locked-down machines. It is not a replacement for professional EDA suites on complex production hardware, and it doesn't replace engineering review.

One data note: designs are processed on PCBEditor's servers, and prompts and design intent are sent to the hosted model provider as part of the generation process. Footprint and symbol data comes from KiCad libraries (licensed CC-BY-SA-4.0).

Pre-Order Checklist

Use this as your final gate before sending to fab:

1. Check every component selection and pin assignment against the datasheet — especially power, ground, enable, and boot pins.
2. Confirm the schematic before generating copper. Re-generating means re-reviewing.
3. Confirm the unrouted net list is empty.
4. Open the .kicad_pcb file in KiCad and run a design rule check using your fab's rules.
5. Inspect the Gerber and drill files in a viewer: layer count, board outline, and hole positions.
6. Compare minimum trace width, clearance, drill size, and annular ring against your fab's process capability table.
7. Run a dedicated signal integrity review for any high-speed or RF nets.
8. Order a small prototype run before going to volume production.

The underlying logic of this checklist always comes back to that same division of responsibility: the model handles judgment, the engine handles measurement. Your review should focus on the part where the model can be wrong and geometry checks won't catch it.