Advanced Packaging
Advanced packaging technologies in semiconductor manufacturing, such as TSMC CoWoS and Intel EMIB, used to interconnect multiple chips or chiplets at high density, improving performance and integration.
Timeline (last 90 days)
Advanced packaging lines have long construction cycles and expensive equipment, and their capacity ramp-up speed often cannot keep pace with the growth in AI chip demand, becoming another major bottleneck in the supply chain.
The key variables determining whether AMD can deliver on its $17 billion guidance include the allocation of advanced-node foundry capacity, the ramp-up of advanced packaging capacity, and the maturity of its software ecosystem.
Advanced packaging is one of the key technology paths for extending Moore's law, including 2.5D/3D integration, through-silicon vias (TSVs), chiplet interconnect, and fan-out wafer-level packaging.
In the AI chip field, because single-chip area is limited by the lithography mask size, integrating multiple chiplets through advanced packaging has become the mainstream approach for increasing computing power and bandwidth.
The equipment involved in advanced packaging (such as temporary bonding/debonding, redistribution-layer lithography, and inspection equipment) is expensive and has a narrow process window, and most university facilities possess only some of these capabilities, so cross-institutional collaboration to complete the packaging process flow is a common need.
CoWoS (Chip on Wafer on Substrate) is an advanced packaging technology developed by TSMC that achieves higher bandwidth and lower power consumption by integrating multiple chips on a single substrate.
All Facts (6)
Advanced packaging lines have long construction cycles and expensive equipment, and their capacity ramp-up speed often cannot keep pace with the growth in AI chip demand, becoming another major bottleneck in the supply chain.
50%UnverifiedThe key variables determining whether AMD can deliver on its $17 billion guidance include the allocation of advanced-node foundry capacity, the ramp-up of advanced packaging capacity, and the maturity of its software ecosystem.
50%UnverifiedAdvanced packaging is one of the key technology paths for extending Moore's law, including 2.5D/3D integration, through-silicon vias (TSVs), chiplet interconnect, and fan-out wafer-level packaging.
50%UnverifiedIn the AI chip field, because single-chip area is limited by the lithography mask size, integrating multiple chiplets through advanced packaging has become the mainstream approach for increasing computing power and bandwidth.
50%UnverifiedThe equipment involved in advanced packaging (such as temporary bonding/debonding, redistribution-layer lithography, and inspection equipment) is expensive and has a narrow process window, and most university facilities possess only some of these capabilities, so cross-institutional collaboration to complete the packaging process flow is a common need.
50%UnverifiedCoWoS (Chip on Wafer on Substrate) is an advanced packaging technology developed by TSMC that achieves higher bandwidth and lower power consumption by integrating multiple chips on a single substrate.
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