Former Graphcore President Lu Tao Joins MemSilicon: LPU Aims to Run Full-Fledged Models at High-Speed Rail Prices

The AI inference chip race has gained another heavyweight player. MemSilicon (铭芯启睿) has completed a Series A round of over 400 million RMB, led by Boyuan Capital, with participation from Bosch Ventures, Chuangling Capital, miHoYo, Zhongguancun Science City Company, and GigaDevice. Existing investors Fuhong Investment, CDB Venture Capital, Hengyu Capital, Jinqiu Fund, Shunxi Fund, Xiaomi Strategic Investment, and CAS Star continued to increase their stakes. Most notably, Lu Tao, former President and Greater China General Manager of Graphcore, has joined as CEO and co-founder, leading the launch of the company's first-generation LPU (Language Processing Unit) development.

Why Lu Tao Chose to Join Now

Lu Tao has more than two decades of experience in the semiconductor industry, having served as General Manager of Cavium China and Vice President of Xizhi Technology, covering areas including Arm server CPUs, AI processor IPUs based on large-SRAM architecture, and silicon photonics. His connection with MemSilicon began in 2024 when the company was founded—at that time, MemSilicon invited him to serve as CEO, but he declined.

The turning point came at GTC. Watching Jensen Huang unveil products, Lu Tao felt a strong nostalgia for the days of competing head-on with chip giants: challenging NVIDIA at Graphcore, building server CPUs against Intel at Cavium, and developing switch chips against Broadcom. Starting a company from scratch was an option, but he did the time math: assembling a team, determining the architecture, and closing financing would take six to nine months even in a hot capital market, and he wasn't confident this wave of enthusiasm would last. Joining MemSilicon would let him get started faster.

Another key factor was MemSilicon's technical foundation. The team originates from the team of Academician Liu Ming at the Chinese Academy of Sciences, with over two decades of memory technology accumulation. Beyond RRAM, they also have research foundations in SRAM, MRAM, DRAM, and other areas. Before Lu Tao joined, MemSilicon had already decided to extend from memory to computing, which恰好 gave Lu Tao the space to independently drive computing products.

Graphcore and IPU: Graphcore is a UK-based AI chip startup whose core product, the IPU (Intelligence Processing Unit), uses a large-scale on-chip SRAM architecture, emphasizing fine-grained parallelism and graph computing. It was once regarded as one of the most closely watched challengers to NVIDIA's GPU in AI training/inference. Lu Tao served as Graphcore's President and Greater China General Manager, responsible for its China market commercialization—an experience that exposed him to both architecture implementation and customers' willingness to pay.

GTC: The NVIDIA GPU Technology Conference, NVIDIA's annual flagship event for launching new GPUs, software stacks, and ecosystem roadmaps, also regarded as a bellwether for AI compute. Lu Tao decided to join MemSilicon after seeing Jensen Huang's product launch at GTC, illustrating how top vendors' product cadence directly influences entrepreneurs' timing judgments.

The Dual Capability of "Know-How" and "Know-Why"

After joining, Lu Tao quickly assembled a core LPU team of a dozen or so people, covering hardware, compilers, and system software. He particularly values the experience gained from real-world engagements with top customers at Graphcore—how new architectures get deployed, and what made successes and failures happen.

Lu Tao sums up the team's capabilities in two words: know-how and know-why. They know how to build the chip, and they also understand why they're building it and what value they ultimately need to deliver to users. In his view, there are already enough GPU and NPU companies; a new team must define its architecture starting from unsolved problems. "Building an AI chip is very difficult, and selling it is even harder." This is a judgment he repeatedly emphasizes.

Product Goal: Full-Fledged Models at High-Speed Rail Prices

MemSilicon's first LPU targets complete models with trillions of parameters, without relying on quantization, speculative decoding, or similar techniques, aiming for 1,000 tokens per second per user.

Beyond speed, there's price. Lu Tao uses high-speed rail as an analogy: if a regular ticket costs 200 RMB but a high-speed rail ticket costs 2,000 RMB, it's hard to achieve widespread adoption. High-speed inference can be more expensive than regular service, but the premium must be limited. "It won't be a niche in the future—it will be mainstream." He hopes that through joint innovation in memory, computing, and interconnect, the LPU can run full-fledged models, achieve high-speed token generation, and deliver leapfrog cost-effectiveness.

The Graphcore IPU that Lu Tao helped commercialize used a large-SRAM architecture. SRAM provides high bandwidth and low latency, but when facing models with trillions of parameters, capacity becomes a hard constraint; adding more chips to accommodate the model introduces cost, power, and latency overhead from cross-chip interconnect. MemSilicon's approach is to retain SRAM's speed advantage while introducing the capacity advantages of other media, using fewer chips to host large models and controlling interconnect costs.

You may not have noticed: the first-generation LPU will not use RRAM, but rather more mature memory media; RRAM still needs to overcome capacity challenges before it can be combined with computing products in the future. Currently, MemSilicon is in discussions with leading cloud service providers and large model companies. Lu Tao expects to deliver computing products to customers within the next two to three years, while simultaneously advancing high-capacity RRAM development.

LPU (Language Processing Unit): LPU is not a unified standard term; it generally refers to processors specifically optimized for large language model inference, emphasizing low latency, high token throughput, and deterministic execution rather than general-purpose training capability. Unlike GPUs that rely on high-bandwidth memory and massive parallel threads, the LPU approach often reduces inference latency through more aggressive on-chip storage, compilation scheduling, and dataflow design. MemSilicon's first LPU is positioned precisely for inference, with the goal of achieving high-speed token generation on full-parameter models.

Full-Fledged Models, Quantization, and Speculative Decoding: "Full-fledged model" refers to a complete-precision model that has not undergone quantization compression or parameter pruning. Quantization (such as FP8/INT8) can reduce memory usage and bandwidth pressure but may lose accuracy; speculative decoding uses a small model to draft and a large model to verify, accelerating generation as a software-level optimization. MemSilicon's proposal to "not rely on quantization and speculative decoding" means its speed goals must be delivered by the hardware architecture and memory bandwidth itself, rather than through model compression or algorithmic tricks—placing higher demands on chip capacity and bandwidth.

RRAM (Resistive RAM): RRAM is an emerging non-volatile memory technology that stores data by applying voltage to change the resistance state of a medium. It theoretically offers advantages such as high density, low power consumption, and compatibility with CMOS back-end processes, and is considered one of the candidate media for compute-in-memory. However, capacity scaling, yield, consistency, and endurance remain engineering challenges. MemSilicon's team originates from Academician Liu Ming's team at the Chinese Academy of Sciences, with over two decades of RRAM accumulation; the article explicitly states that the first-generation LPU will not use RRAM but instead adopt more mature media, indicating that RRAM is still constrained by capacity and needs to be tackled before being combined with computing products.

The Capacity Bottleneck of SRAM Architecture: SRAM is fast, low-latency, and high-bandwidth, but has low capacity per unit area and high cost. The Graphcore IPU's large-SRAM architecture has clear advantages on small and medium models, but when facing models with trillions of parameters, single-chip SRAM capacity is far from sufficient to hold the model, necessitating more chips and reliance on cross-chip interconnect, which in turn brings cost, power, and communication latency overhead. MemSilicon's approach is to retain SRAM speed while introducing capacity from other media—essentially a hybrid design at the memory hierarchy level to alleviate this bottleneck.

Memory and Computing on the Same Team Is the Real Differentiation

The AI chip race is crowded today. MemSilicon's differentiation lies not in any single technology, but in bringing memory devices, process accumulation, computing architecture, software, and industrialization experience into the same team. Lu Tao's joining gives the company's technical accumulation a chance to extend from memory into a complete computing system, and leaves room for continuous evolution toward "full-fledged models at high-speed rail prices."

From an industry perspective, whether this path can succeed depends on two variables: first, whether the hybrid memory media approach can deliver the balance of speed and capacity under real workloads; second, whether customers are willing to pay a limited premium for high-speed inference. The former is an engineering problem, the latter a market problem—and Lu Tao's experience at Graphcore happens to cover both ends.

One-line Summary

MemSilicon completes over 400 million RMB Series A; former Graphcore President Lu Tao becomes CEO, leading development of high-speed inference LPUs for full-fledged models.

Paragraph Summary

MemSilicon has completed a Series A round of over 400 million RMB, led by Boyuan Capital with participation from Bosch Ventures, miHoYo, GigaDevice, and continued support from existing investors. Former Graphcore President and Greater China General Manager Lu Tao has joined as CEO and co-founder, leading the first-generation LPU development. Lu Tao values MemSilicon's memory technology accumulation from Academician Liu Ming's CAS team and the company's room to extend from memory to computing. The first LPU targets complete models with trillions of parameters, without relying on quantization or speculative decoding, aiming for 1,000 tokens per second per user and "high-speed rail pricing" with limited premium for high-speed inference. The first-generation product will not use RRAM, instead combining SRAM's speed with the capacity advantages of other media to reduce chip count and interconnect costs. MemSilicon's differentiation lies in having memory, computing, software, and industrialization experience on the same team.