RTL

RTL is the key abstraction layer in chip design between system architecture and physical layout, describing in hardware description language the logic of data flow between registers.

Delphi mitigates dynamic library compatibility issues through package version numbers and runtime library (RTL) binding.

RTL (register transfer level) is a high-level abstraction of chip design, using hardware description languages (such as Verilog or VHDL) to describe the logic of data flowing between registers; GDSII is the final delivery format for a chip's physical layout, containing the geometric shape information of each mask layer and can be sent directly to a wafer fab for tape-out.

Synthesis is the automated conversion of RTL code into a gate-level netlist composed of standard cell libraries, completed by EDA tools.

RTL (Register Transfer Level) is the core abstraction layer in chip logic design, where engineers use HDL to describe how data flows and transforms between registers without involving specific transistor implementation.

RTL code is almost never publicly released in open-source form, and high-quality RTL corpora searchable on GitHub are extremely limited.

Most current LLM chip design agent approaches work directly at the low-level abstraction of Register Transfer Level (RTL).

By introducing High-Level Synthesis (HLS) as the agent's working level combined with RTL-level refinement, the research team achieved an average geometric mean speedup of 2.6× over direct RTL design on multi-task benchmarks.

The research team designed and compared four workflows: direct RTL design, agent-based HLS design, post-compilation HLS refinement, and post-HLS RTL refinement.

The paper's core contribution, AHRR (Agent-based HLS with RTL Refinement), combines agent-based HLS design with post-HLS RTL refinement, forming a workflow that first constructs the design at a high level of abstraction and then returns to the RTL layer to reclaim low-level optimization opportunities.

The value of post-HLS RTL refinement lies in its ability to re-exploit optimization opportunities that can only be realized at the lower level.

Verilog and VHDL are the most commonly used RTL description languages.

RTL has a far lower error tolerance than software; a logic error in a taped-out chip means millions of dollars in losses, which is why AI-generated RTL must undergo rigorous formal verification.

The RTL code for a modern SoC can reach several million lines.

RTL code is typically written in hardware description languages such as Verilog or VHDL.

RTL (Register Transfer Level) is a critical abstraction layer in chip design that sits between algorithmic description and gate-level circuits.

Previous academic work on automatic RTL code generation is generally limited to small modules or specific circuit structures, and the generated results often require manual correction before passing synthesis and verification.

An AI system, with only two human architects writing hardware specification documents, automatically generated performance models, RTL code, a UVM verification environment, formal proofs, firmware, and a kernel — completing the entire process within two weeks, with no human intervention below the specification layer.