PCIe

CXL is an open interconnect standard based on the PCIe physical layer that allows high-speed, low-latency cache-coherent communication between CPUs and various accelerators and memory expansion devices.

The core goal of NVLink is to break through the bandwidth limitations of the traditional PCIe bus and allow multiple GPUs to communicate directly at extremely high speeds.

Traditional PCs' discrete VRAM offers higher bandwidth, but capacity is limited by the graphics card model, and once a model exceeds VRAM it must be moved over the PCIe bus, drastically reducing speed.

In heterogeneous backends, PCIe bandwidth is typically far lower than NVLink and will become the bottleneck for cross-device scheduling; placing the draft model on a device under the same PCIe root complex as the target model, or directly on the CPU, is often more worthwhile than moving data across NUMA nodes.

以隐藏维度 8192 的 70B 模型、batch size = 1 为例，每生成一个 token 穿越 PCIe 的总数据量只有几 MB。

PCIe Gen4 x16 bandwidth is approximately 64GB/s, which often becomes a hard bottleneck in memory offloading scenarios.

EPYC平台通常提供业界领先的内存通道数和PCIe通道数

System-bound means non-GPU factors such as CPU scheduling, PCIe transfer, and Python interpreter overhead become the bottleneck, requiring system-level measures such as asynchronous execution and reducing synchronization points.

Vendors have already released PCIe-to-ISA adapter cards based on FPGAs, enabling legacy ISA industrial cards to be inserted into modern server motherboards and operated.

By routing inter-GPU data exchange through NVLink and bypassing the host PCIe channel, reliance on host bandwidth in inference scenarios can be reduced.

Due to the laptop motherboard's lack of standard PCIe slots, one 3090 is connected via the WWAN slot at PCIe Gen4 x1, while the other borrows the SSD slot running at Gen2 x4.

NVLink speed degradation or fallback to PCIe mode can reduce intra-node communication speed by several times, yet OS-level health checks will still mark the link as normal.

Mini PCs lack PCIe expansion capability, making it impossible to insert a discrete GPU, professional network card, or HBA card.

Compared to PCIe, NVLink provides higher bidirectional bandwidth and lower latency.

Traditional auto-routers often fail to satisfy the precise constraints of high-speed digital circuits (such as DDR4/DDR5 memory interfaces and PCIe buses), including trace length matching, impedance control, and crosstalk isolation.