HBM4
The fourth-generation High Bandwidth Memory standard, featuring an interface width expanded to 2048-bit and a theoretical peak bandwidth exceeding 1.5 TB/s. HBM4 introduces a new architecture that separates the logic base die from the memory stack, enabling deep co-design with GPUs and NPUs.
Timeline (last 90 days)
Maia 300 is configured with 8 HBM4 stacks, providing 288GB of capacity and 18TB/s of bandwidth, which is 2.5 times the memory bandwidth and 33% more capacity than Maia 200.
Maia 300 is equipped with 8 HBM4 memory stacks, uses compute chiplets manufactured on TSMC's N2P process, and is deployed in the form of 96-accelerator racks.
HBM4 is planned to increase the number of stacked layers to 16–20, achieving approximately 4 TB of capacity per square centimeter, but each layer receives only about 20% of the single-chip bandwidth.
Jalapeño uses HBM4 memory to deliver 15.4 TB/s of bandwidth, consuming half the power and offering twice the bandwidth of Blackwell at a similar memory capacity.
Samsung Electronics plans to more than double the production volume of its next-generation high-bandwidth memory (HBM4 and HBM4E) DRAM.
HBM4 introduces a new architecture that separates the logic base die from the memory stack, allowing chip manufacturers to integrate custom logic directly into the bottom of the HBM.
HBM4 increases the bottom interface bus width from the 1024-bit of HBM3E to 2048-bit.
HBM4 is the next-generation standard of the HBM specification, offering improvements over the previous generation HBM3E in interface bus width, bandwidth density, and energy efficiency.
All Facts (8)
Maia 300 is configured with 8 HBM4 stacks, providing 288GB of capacity and 18TB/s of bandwidth, which is 2.5 times the memory bandwidth and 33% more capacity than Maia 200.
50%UnverifiedMaia 300 is equipped with 8 HBM4 memory stacks, uses compute chiplets manufactured on TSMC's N2P process, and is deployed in the form of 96-accelerator racks.
50%UnverifiedHBM4 is planned to increase the number of stacked layers to 16–20, achieving approximately 4 TB of capacity per square centimeter, but each layer receives only about 20% of the single-chip bandwidth.
50%UnverifiedJalapeño uses HBM4 memory to deliver 15.4 TB/s of bandwidth, consuming half the power and offering twice the bandwidth of Blackwell at a similar memory capacity.
50%UnverifiedHBM4 introduces a new architecture that separates the logic base die from the memory stack, allowing chip manufacturers to integrate custom logic directly into the bottom of the HBM.
50%UnverifiedHBM4 increases the bottom interface bus width from the 1024-bit of HBM3E to 2048-bit.
50%UnverifiedHBM4 is the next-generation standard of the HBM specification, offering improvements over the previous generation HBM3E in interface bus width, bandwidth density, and energy efficiency.
50%UnverifiedSamsung Electronics plans to more than double the production volume of its next-generation high-bandwidth memory (HBM4 and HBM4E) DRAM.
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